Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Chapter 4: Host/DCR Bus Interfaces
Reading the PHY Registers using MDIO
To read from a configuration register either in the Ethernet MAC PCS/PMA layer or from
an external PHY, the user must perform the following sequence of operations on the DCR
bus:
1. Write to the dataRegLSW register with the PHYAD and register to be accessed. This
value should be formatted as shown in Figure 4-9.
2. Write to the cntlReg register with the decode address for MDIO transaction (0x3B4)
and the write enable bit cleared to indicate a read operation. Use
EMAC0_DCRBASEADDR to perform the transaction on the EMAC0 MDIO interface
and EMAC1_DCRBASEADDR to perform the transaction on the EMAC1 MDIO
interface.
3. Poll the RDYstatus_e# register until the MDIO Write-Ready bit is set or wait until the
DCRHOSTDONEIR interrupt is asserted.
4. Read the PHY register contents from the dataRegLSW.
To read PHYAD 0x1 and PHY register 0x4 through the EMAC0 MDIO interface, MDIO
must be enabled by writing to the management configuration register with the clock
divider for MDC, as described in “Writing to an Ethernet MAC Configuration Register.”
// Write the PHY address and PHY register to be accessed to the
// dataRegLSW register
dcr_write(EMAC0_DCRBASEADDR + 1, (0x1