Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Appendix C: Virtex-4 to Virtex-5 FPGA Enhancements DCR Bus Modifications In Virtex-5 devices, the DCR bus signals can be directly accessed in the FPGA logic; whereas in Virtex-4 devices, these signals are inaccessible because they are directly connected to the PowerPC processor. The PowerPC 405 processor is the current standard in Virtex-4 FPGAs. Changing processors requires some changes to the DCR acknowledge operation. These changes are backward-compatible. In the XPS_LL_TEMAC soft core that is delivered through the XPS tool, the DCR bus is not exposed. The core contains a bridge to enable the control of the Ethernet MAC via the PLB v4.6 interface. For more information on the PLB v4.6 interface, see DS531, Processor Local Bus (PLB) v4.6 (v1.00a). The DCR register definitions have been modified. In Virtex-4 FPGA designs, the DCR registers holds information about EMAC0 and EMAC1 in the same register. In Virtex-5 FPGA designs, information on each EMAC is be accessed specifically through the EMAC0_DCRBASEADDR and EMAC1_DCRBASEADDR registers. There have also been changes to the DCR register addressing. This change requires Virtex-4 FPGA designs to update the address schemes. In Virtex-4 FPGA designs, the DCR bus is responsible for decoding the user-defined DCR_BASEADDR to enable the EMAC host interface access. In Virtex-5 FPGA designs, the interface only responds to accesses made to addresses matching the EMAC#_DCRBASEADDR attributes. Table C-1 shows the modifications to the DCR register addressing. Clocking Scheme Enhancements Host Clock Table C-1: DCR Register Address Modifications DCR Register Virtex-4 FPGA Address Virtex-5 FPGA Address dataRegMSW DCR_BASEADDR_00 EMAC#_DCRBASEADDR_00 dataRegLSW DCR_BASEADDR_01 EMAC#_DCRBASEADDR_01 cntlReg DCR_BASEADDR_10 EMAC#_DCRBASEADDR_10 RdyStatus DCR_BASEADDR_11 EMAC#_DCRBASEADDR_11 The Virtex-4 HOSTCLK input clock has to be supplied at all times even if the host interface is not used. In Virtex-5 designs, when neither the generic host bus nor the DCR bus are enabled, this clock input can be connected to logic 0. Advanced Clocking Schemes In the Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC, two advanced clocking schemes are available, named “Clock Enables” and “Byte PHY.” In Virtex-4 FPGA designs, these clocking schemes can be implemented in the FPGA logic but for a smaller subset of physical interface configurations. “Advanced Clocking Schemes,” page 208 provides further details on theses clocking schemes. 218 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Clock Enables Modifications Related to the Physical Interface Virtex-4 FPGA clock enable signals are created in the FPGA logic, resulting in a clocking scheme that halves the global clock usage when using the MII physical interface for 10 Mb/s or 100 Mb/s. The Virtex-5 FPGA clock enables are provided by the Ethernet MAC to the FPGA logic, and their use has extended to cover MII, GMII, and RGMII interfaces at all three Ethernet speeds. Byte PHY For Virtex-4 FPGA designs, a solution is possible in the FPGA logic that halves the global clock usage when using the GMII/MII physical interface at all three speeds. But, it only supports full-duplex mode. In Virtex-5 FPGA designs, the Byte PHY functionality is extended to cover the GMII/MII, again at all three speeds but supports both full- and half-duplex modes. Modifications Related to the Physical Interface Collision Handling In Virtex-4 FPGA designs, the GMII_COL/MII_COL signal (half-duplex mode collision indicator from GMII/MII interface) had to be lengthened in the FPGA logic. In Virtex-5 FPGA designs, the signal can be input directly to the PHYEMAC#COL port of the Ethernet MAC. RGMII Version 2.0 Clock Management Port Map Changes In Virtex-5 FPGA designs, an ODELAY design element can be used to simplify the generation of 2 ns skew between the transmit clock and data at the FPGA device pads. This is part of the IOB and clock logic that can be used with the Ethernet MAC to meet the RGMII v2.0 physical interface specification. The following name changes occurred to clarify functionality: EMAC#CLIENTTXGMIIMIICLKOUT changed to EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXGMIIMIICLKIN changed to PHYEMAC#TXGMIIMIICLKIN The following ports were removed: EMAC#CLIENTRXDVREG6: In Virtex-4 devices, this signal is reserved and not used. TIEEMAC#CONFIGVEC[79:0]: This port has been replaced by attributes TIEEMAC#UNICASTADDR[47:0]: This port has been replaced by an attribute. The following port was added to enable advanced clocking schemes to be used: EMAC#SPEEDIS10100 TEMAC User Guide www.xilinx.com 219 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217: R Virtex-4 to Virtex-5 FPGA Enhance
Page 221 and 222: R Additional Attributes Table C-2:
Page 223 and 224: R Appendix D Differences between So
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