Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Using the DCR Bus to Access Statistics Registers
Using the DCR Bus to Access Statistics Registers
When the DCR bus interface of the Ethernet MAC is controlled by an embedded processor,
the host interface and DCR bridge of the Ethernet MAC allow DCR bus accesses to control
the unused host bus pins. The Ethernet MAC host bus interface can then access the
statistics counters in the FPGA logic, controlled by register accesses on the DCR bus.
The host bus I/O signals of the Ethernet MAC are enabled for statistics counter access
when a DCR read operation is made to address codes 0x000 to 0x02F and 0x040 to
0x04F inclusive (Table 4-15, page 103 describes the DCR address code space). This use of
the host bus I/O signals provides a means of accessing the FPGA logic from the processor
with space for 64 addresses.
When the DCR bus is instructed to access registers in this address code region, the DCR
bridge translates the DCR commands into generic host read signals on the host bus I/O
signals. The DCR transaction is encoded on the host bus signals HOSTRDDATA[31:0] and
HOSTMIIMRDY as described in Table 4-23 and Figure 4-10. These signals can access
statistics counters in the same way as if a stand-alone host bus is used. The statistics values
read from statistics counters are captured from the host bus signals HOSTWRDATA[31:0]
as shown in Figure 4-10. The data read from the host bus can then be accessed by reading
the DCR data registers.
Figure 7-2 shows how to integrate the Ethernet MAC with the LogiCORE Ethernet
Statistics block, where the LogiCORE Ethernet statistics counters are accessed via the DCR
bus. DS323, LogiCORE Ethernet Statistics Data Sheet, provides a full description of the
Ethernet Statistics LogiCORE block. Figure 7-2 illustrates how to connect LogiCORE
Ethernet Statistics blocks to both Ethernet MACs within the Ethernet MAC block. If
statistics are required for only one Ethernet MAC, then the multiplexing between the
statistics cores is simply replaced with a straight-through connection.
An example of how to read from the statistics counters through the DCR bus is provided in
the example in “Accessing FPGA Logic via Unused Host Bus Pins,” page 113.
TEMAC User Guide www.xilinx.com 201
UG194 (v1.10) February 14, 2011