Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 4: Host/DCR Bus Interfaces Table 4-11: Address Table Access (Word 0) 0x388 MSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GENERAL_ADDRESS[31:0] Bit Description Default Value R/W [31:0] General Address [31:0]. The general address bits [31:0] are temporarily deposited into this register for writing into a general address register. When a read from an address register has been performed, the address bits [31:0] are accessible from this register. The address is ordered so the first byte transmitted/received is the lowest positioned byte in the register; for example, a MAC address of AA-BB-CC- DD-EE-FF is stored in address [47:0] as 0xFFEEDDCCBBAA. Table 4-12: Address Table Access (Word 1) 0x38c MSB 96 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 LSB All 0s R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RNW RESERVED ADDR GENERAL_ADDRESS[47:32] Bit Description Default Value R/W General Address (Word 1) [15:0] General Address [47:32]. The general address bits [47:32] are temporarily deposited into this register for writing into a general address register. [17:16] Address Table address. This two-bit vector is used to choose the general address register to access. 00 = General Address Register 0 01 = General Address Register 1 10 = General Address Register 2 11 = General Address Register 3 [22:18] Reserved. – [23] Address Table read enable (RNW). When this bit is 1, a general address register is read. When this bit is 0, a general address register is written with the address set in the general address table register. [31:24] Reserved. – LSB All 0s R/W All 0s R/W 0 R/W R
R Table 4-13: Address Filter Mode 0x390 MSB Using the Host Bus Using the Host Bus 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PM To access the host interface using the host bus, the DCREMACENABLE signal should be tied to logic 0. When using the host bus, the type of transaction initiated is dependant on the host bus signals HOSTMIIMSEL, HOSTADDR[9], and HOSTEMAC1SEL. Table 4-14 shows the access method required for each transaction type. Clocking Requirements RESERVED Bit Description Default Value R/W Address Filter Mode [30:0] Reserved. – [31] Promiscuous Mode enable. When this bit is 1, the Address Filter block is disabled. When this bit is 0, the Address Filter block is enabled. Table 4-14: Host Bus Transaction Types 1: When EMAC#_ADDRFILTERENABLE is FALSE 0: When EMAC#_ADDRFILTERENABLE is TRUE Transaction R/W HOSTEMAC1SEL HOSTMIIMSEL HOSTADDR[9] HOSTOPCODE[1]HOSTOPCODE[0] EMAC0 Configuration/Address Filter Read 0 0 1 1 X Write 0 0 1 0 X EMAC0 MDIO access Read 0 1 X 1 0 EMAC1 Configuration/Address Filter Write 0 1 X 0 1 Read 1 0 1 1 X Write 1 0 1 0 X EMAC1 MDIO access Read 1 1 X 1 0 Write 1 1 X 0 1 The HOSTCLK can operate at speeds of up to 125 MHz. This clock can be tied to a usersupplied, 125 MHz input clock to save on clock resources, such as the 125 MHz clock provided into the PHYEMAC#GTXCLK port (see Appendix C, “Virtex-4 to Virtex-5 FPGA Enhancements”). The host clock (HOSTCLK) is used to derive the MDIO clock, MDC. Configuring the Ethernet MAC to derive MDC is detailed in “Accessing MDIO through the Host Interface,” page 119. TEMAC User Guide www.xilinx.com 97 UG194 (v1.10) February 14, 2011 LSB R/W
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95: R Table 4-9: Unicast Address (Word
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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R Gigabit Media Independent Interfa
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R Gigabit Media Independent Interfa
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R Reduced Gigabit Media Independent
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GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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