Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

HOSTCLK
HOSTMIIMSEL
HOSTREQ
HOSTOPCODE[1:0]
HOSTEMAC1SEL
HOSTADDR[9:0]
HOSTWRDATA[31:0]
HOSTMIIMRDY
HOSTRDDATA[31:0]
DCREMACENABLE
DCRHOSTDONEIR
R
Figure 4-2 shows the block diagram of the host interface.
DCR Bus
Ethernet MAC Block
FPGA Logic
Host
Interface
Figure 4-2: Ethernet MAC Host Interface Block Diagram
Ethernet MAC Register Descriptions
To access management registers in the PCS/PMA sublayer, the MDIO interface is used.
The MDIO interface is described in detail in Chapter 5, “MDIO Interface,” and access to the
MDIO through the host interface is discussed later in this chapter.
Ethernet MAC Register Descriptions
MIIMSEL0
REQ0
OPCODE0
ADDR0
WRD0
MIIMRDY0
RDD0
(All internal signals)
MIIMSEL1
REQ1
OPCODE1
ADDR1
WRD1
MIIMRDY1
RDD1
EMAC0
EMAC1
UG194_4_02_0080409
Each Ethernet MAC has twelve configuration and address filter registers. These registers
are accessed through the host interface and can be written to at any time. Both the receiver
and transmitter logic only responds to configuration changes during Inter Frame gaps. The
configurable resets are the only exception that take effect immediately. Writes made to
address filter registers take effect immediately. To avoid corruption of incoming frames,
writing to these registers should be made only while frame reception is not in progress.
Table 4-1: Ethernet MAC Register Addresses
Configuration
and
Address Filter
Configuration
and
Address Filter
PCS/ PMA0
Management
Registers
PCS/ PMA1
Management
Registers
TEMAC User Guide www.xilinx.com 87
UG194 (v1.10) February 14, 2011
MDIO
MDIO
ADDRESS[9:0] Register Description
0x200 Receiver Configuration (Word 0)
0x240 Receiver Configuration (Word 1)
0x280 Transmitter Configuration
0x2C0 Flow Control Configuration
0x300 Ethernet MAC Mode Configuration
0x320 RGMII/SGMII Configuration