Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface CLKFB CLKIN DCM Tx and Rx Client Logic CLK0 CLKDV CLKDV_DIVIDE = 2.0 BUFG BUFG X X Ethernet MAC PHYEMAC#GTXCLK PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXCLIENTCLKIN EMAC#CLIENTTXCLIENTCLKOUT PHYEMAC#MIITXCLK CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT PHYEMAC#RXCLK CLIENTEMAC#DCMLOCKED 125 MHz IBUFDS GTX Transceiver TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 UG194_6_23_031109 Figure 6-23: 1000BASE-X PCS/PMA (8-Bit Data Client) Clock Management in a TXT and FXT Device The CLKIN inputs to the RocketIO serial transceiver must be connected to an external, high-quality differential reference clock of frequency of 125 MHz. A 125 MHz clock source is then provided to the FPGA logic from the REFCLKOUT output port of the RocketIO serial transceiver. This is connected to the CLKIN input of a DCM, as illustrated in Figure 6-23. The CLK0 output of the DCM should then be routed to the PHYEMAC#GTXCLK of the Ethernet MAC via a BUFG. The clock is also routed to the TXUSRCLK2 and RXUSRCLK2 inputs of the GTX transceiver. Additionally, this global clock can be used for both receiver and transmitter client logic, and it, therefore, must be routed back to the Ethernet MAC through the CLIENTEMAC#RXCLIENTCLKIN and CLIENTEMAC#TXCLIENTCLKIN input ports. A second 62.5 MHz clock is output from the DCM on the CLKDV port. This should be used to clock the TXUSRCLK and RXUSRCLK inputs of the GTX transceiver. The PLLLKDET signal from the RocketIO serial transceiver (indicating that its internal PLLs have locked) is routed to the CLIENTEMAC#DCMLOCKED input port of the Ethernet MAC. This ensures that the state machines of the Ethernet MAC are held in reset until the RocketIO serial transceiver has locked, and its clocks are running cleanly. 172 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 X BUFG CLKIN REFCLKOUT PLLLKDET R
R DCM BUFG CLKFB CLK0 CLKIN CLKFX BUFG Locked = 2XCLKFX_MULTIPLY CLKFX_DIVIDE = 1 Tx and Rx Client Logic 1000BASE-X PCS/PMA As described in Appendix B, “Ethernet MAC Clocks,” the following clock signals are unused: EMAC#CLIENTRXCLIENTCLKOUT EMAC#CLIENTTXCLIENTCLKOUT EMAC#PHYTXGMIIMIICLKOUT PHYEMAC#TXGMIIMIICLKIN PHYEMAC#MIITXCLK PHYEMAC#RXCLK The outputs can be left unconnected, and inputs should be tied to Low. 16-Bit Data Client Figure 6-24 shows the clock management used with the 1000BASE-X PCS/PMA interface and a 16-bit data client in a TXT and FXT device. This mode supports 2.5 Gb/s line rates. AND Ethernet MAC PHYEMAC#GTXCLK PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#MIITXCLK CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT PHYEMAC#RXCLK CLIENTEMAC#DCMLOCKED 125 MHz IBUFDS REFCLKOUT PLLLOCK TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 6-24: 1000BASE-X PCS/PMA (16-Bit Data Client) Clock Management in a TXT and FXT Device The CLKIN inputs to the RocketIO serial transceiver must be connected to an external, high-quality, differential reference clock with a frequency of 125 MHz. A clock source matching the reference clock frequency is then provided to the FPGA logic from the REFCLKOUT output port of the RocketIO serial transceiver. This clock is then routed to the CLKIN input of a DCM. CLK0 of the DCM is connected to global clock routing using a BUFG, as illustrated in Figure 6-24. The 125 MHz output of the BUFG is connected to the TEMAC User Guide www.xilinx.com 173 UG194 (v1.10) February 14, 2011 X BUFG GTX Transceiver CLKIN UG194_6_24_080409
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
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R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
Page 215 and 216: R Clock Definitions and Frequencies
Page 217 and 218: R Virtex-4 to Virtex-5 FPGA Enhance
Page 219 and 220: R Clock Enables Modifications Relat
Page 221 and 222: R Additional Attributes Table C-2:
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R Appendix D Differences between So
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