Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Table 3-3: Bit Definitions for the Transmitter Statistics Vector (Cont’d)
TX_STATISTICS_VECTOR Name Description
Receiver Statistics Vector
Statistics Vectors
4 CONTROL_FRAME Asserted if the previous frame has the special
Ethernet MAC control type code 88-08 in the LT
field.
3 UNDERRUN_FRAME Asserted if the previous frame contains an underrun
error.
2 MULTICAST_FRAME Asserted if the previous frame contains a multicast
address in the destination address field.
1 BROADCAST_FRAME Asserted if the previous frame contains a broadcast
address in the destination address field.
0 SUCCESSFUL_FRAME Asserted if the previous frame is transmitted
without error.
Notes:
1. Bits 28:20 of TX_STATISTICS_VECTOR are valid for half-duplex mode only.
CLIENTEMAC#RXCLIENTCLKIN
RX_STATISTICS_VALID
(internal signal)
RX_STATISTICS_VECTOR[26:0]
(internal signal)
EMAC#CLIENTRXSTATSVLD
EMAC#CLIENTRXSTATS[6:0]
RX_STATISTICS_VECTOR contains the statistics for the frame received. It is a 27-bit vector
and an internal signal. This vector is muxed out to a 7-bit signal
EMAC#CLIENTRXSTATS[6:0], as shown in Figure 3-34 , following frame reception. For
standard clock management, the vector is driven synchronously by the receiver clock,
CLIENTEMAC#RXCLIENTCLKIN. For alternative clock management, including the use of
clock enables, the vector is driven synchronously to other RX client logic signals. See
Chapter 6, “Physical Interface,” for relevant clocking networks.
The bit-field definition for the receiver statistics vector is defined in Table 3-4.
[6:0] [13:7] [20:14] [26:21]
Figure 3-34: Receiver Statistics MUX Timing
UG194_3_34_071509
TEMAC User Guide www.xilinx.com 81
UG194 (v1.10) February 14, 2011