Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

R
Operation
Figure 3-30 illustrates the FIFO occupancy over time.
FIFO Occupancy
Full
7/8
1/2
Empty
Flow Control Block
Figure 3-30: Flow Control Implementation Triggered from FIFO Occupancy
The FIFO occupancy of the left Ethernet MAC gradually increases over time due to
the clock tolerances. At point A, the occupancy has reached the threshold of 7/8 full,
triggering the maximum duration pause control frame request.
Upon receiving the pause control frame, the right Ethernet MAC ceases transmission
at point B. The system designer should ensure sufficient space in the FIFO above the
threshold (point A) to allow the transmitter to stop.
After the right Ethernet MAC ceases transmission, the occupancy of the FIFO attached
to the left Ethernet MAC empties. The occupancy falls to the second threshold of 1/2
occupancy at point C, triggering the zero duration pause control frame request (the
pause cancel command).
Upon receiving this second pause control frame, the right hand Ethernet MAC
resumes transmission. To create an efficient system with the maximum possible line
rate, the system designer should ensure sufficient space in the FIFO, below the
threshold (point C), to prevent the FIFO emptying before transmission starts at point
D.
Normal operation resumes, and the FIFO occupancy again gradually increases over
time. At point E, the flow control cycle repeats.
TEMAC User Guide www.xilinx.com 77
UG194 (v1.10) February 14, 2011
A
C
B
D
E
Time
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