Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface GTX_CLK IBUFG TX Client Logic RX Client Logic BUFG X X EMAC# PHYEMAC#GTXCLK PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXCLIENTCLKIN EMAC#CLIENTTXCLIENTCLKOUT EMAC#PHYTXD[3:0] EMAC#PHYTXD[7:4] PHYEMAC#MIITXCLK CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT PHYEMAC#RXCLK PHYEMAC#RXD[3:0] PHYEMAC#RXD[7:4] CLIENTEMAC#DCMLOCKED Notes: 1) A regional buffer (BUFR) can replace this BUFG. In addition, the clock input of IDDR can be driven by a BUFIO. Refer to UG190, Virtex-5 FPGA User Guide for BUFR usage guidelines. Figure 6-13: 1 Gb/s RGMII Hewlett Packard v2.0 Clock Management RGMII_TXC is derived from the Ethernet MAC by routing GTX_CLK to an IOB DDR output register, followed by an ODELAY element and an OBUF (which is then connected to the PHY). The ODELAY element is used to generate 2 ns of skew required between RGMII_TXC and RGMII_TXD at the FPGA device pads. This delay is specified in the Hewlett Packard RGMII Specification, v2.0 to provide setup and hold times on the external interface. RGMII_RXC is generated by the PHY and connected to PHYEMAC#RXCLK via an IBUFG and a BUFG. Fixed-mode IDELAYs are instantiated on the RGMII clock and data lines. These are set to sample a 1 ns setup, 1 ns hold window at the device pads. RGMII_RXC drives all receive logic. The CLIENTEMAC#DCMLOCKED port must be tied High. 156 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 X 1 0 ODDR D1 D2 Q OBUF BUFG (1) IBUFG IDELAY RGMII_TXC RGMII_TXD[3:0] RGMII_RXC IDDR Q1 D IDELAY RGMII_RXD[3:0] Q2 ODDR D1 D2 Q ODELAY IBUF OBUF UG194_6_13_080409 R
GTX_CLK TX Client Logic RX Client Logic R Reduced Gigabit Media Independent Interface (RGMII) RGMII Standard Clock Management for Tri-Speed Operation IBUF RGMII Version 1.3 BUFG BUFG Figure 6-14 shows the tri-speed clock management following the Hewlett Packard RGMII specification v1.3. GTX_CLK must be provided to the Ethernet MAC with a high-quality, 125 MHz clock that satisfies the IEEE Std 802.3-2002 requirements. The EMAC#PHYTXGMIIMIICLKOUT port generates the appropriate frequency derived from GTX_CLK and depending on the operating frequency of the link. It clocks directly the RGMII_TXD ODDR registers. PHYEMAC#GTXCLK EMAC# PHYEMAC#TXGMIIMIICLKIN EMAC#PHYTXGMIIMIICLKOUT CLIENTEMAC#TXCLIENTCLKIN EMAC#CLIENTTXCLIENTCLKOUT CLIENTEMAC#RXCLIENTCLKIN EMAC#CLIENTRXCLIENTCLKOUT EMAC#PHYTXD[3:0] EMAC#PHYTXD[7:4] PHYEMAC#MIITXCLK PHYEMAC#RXCLK PHYEMAC#RXD[3:0] PHYEMAC#RXD[7:4] CLIENTEMAC#DCMLOCKED Notes: 1) A regional buffer (BUFR) can replace this BUFG. In addition, the clock input of IFD can be driven by a BUFIO. Refer to UG190, Virtex-5 FPGA User Guide for BUFR usage guidelines. Figure 6-14: Tri-Mode RGMII v1.3 Clock Management The EMAC#CLIENTTXCLIENTCLKOUT output port connects to the CLIENTEMAC#TXCLIENTCLKIN input port and transmitter client logic in the FPGA logic through a BUFG. The receiver client clocking is similar. TEMAC User Guide www.xilinx.com 157 UG194 (v1.10) February 14, 2011 '1' '0' BUFG (1) D1 D2 D1 D2 ODDR Q ODDR Q OBUF OBUF IBUFG RGMII_TXC RGMII_TXD[3:0] RGMII_RXC IDDR Q1 D IDELAY RGMII_RXD[3:0] Q2 BUFG (1) IDELAY IBUF UG194_6_14_080409
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
Page 105 and 106: R Table 4-18: DCR Control Register
Page 107 and 108: R Using the DCR Bus The IRENABLE_e#
Page 109 and 110: R // Write to the cntlReg_e1 regist
Page 111 and 112: DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 155: R Reduced Gigabit Media Independent
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 165 and 166: FPGA R PCS/PMA Sublayer MAC TX Inte
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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