Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 3: Client Interface CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXD[7:0] CLIENTEMAC#TXDVLD EMAC#CLIENTTXACK CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT Client Underrun DA SA L/T DATA FCS Figure 3-2: Frame Transmission with Client-Supplied FCS UG194_3_02_072206 The timing of an aborted transfer is shown in Figure 3-3. An aborted transfer can occur if a FIFO connected to the client interface empties before a frame is completed. The CLIENTEMAC#TXUNDERRUN signal on the client interface is used to signal to the MAC that an underrun condition exists. When the client asserts CLIENTEMAC#TXUNDERRUN during a frame transmission, the EMAC#PHYTXER output is asserted for one clock cycle to notify the external GMII, RGMII, or MII PHY that the frame is corrupted. If 1000BASE-X PCS/PMA or SGMII mode is operational, the MAC inserts an error code into the current frame to signal corruption. The Ethernet MAC then falls back to idle transmission. The client must requeue the aborted frame for transmission. After an underrun occurs, CLIENTEMAC#TXDVLD must be deasserted for at least one clock cycle before transmission can recommence. CLIENTEMAC#TXDVLD can be deasserted on the same cycle as underrun is asserted. There is no requirement to deassert CLIENTEMAC#TXDVLD when underrun is asserted; it can be deasserted later. 54 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXD[7:0] CLIENTEMAC#TXDVLD EMAC#CLIENTTXACK CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT EMAC#PHYTXER Back-to-Back Transfers CLIENTEMAC#TXCLIENTCLKIN CLIENTEMAC#TXD[7:0] CLIENTEMAC#TXDVLD EMAC#CLIENTTXACK CLIENTEMAC#TXUNDERRUN EMAC#CLIENTTXCOLLISION EMAC#CLIENTTXRETRANSMIT Transmit (TX) Client: 8-Bit Interface (without Clock Enables) DA SA L/T DATA Figure 3-3: Frame Transmission with Underrun UG194_3_03_072206 Back-to-back transfers can occur when the Ethernet MAC client is ready to transmit a second frame of data immediately following completion of the first frame. In Figure 3-4, the end of the first frame is shown on the left. At the clock cycle immediately following the final byte of the first frame, CLIENTEMAC#TXDVLD is deasserted by the client. One clock cycle later, CLIENTEMAC#TXDVLD is asserted High, indicating that the first byte of the destination address of the second frame is awaiting transmission on CLIENTEMAC#TXD. Figure 3-4: Back-to-Back Frame Transmission DA SA UG194_3_04_072206 When the Ethernet MAC is ready to accept data, EMAC#CLIENTTXACK is asserted and the transmission continues in the same manner as the single frame case. The Ethernet MAC defers the assertion of EMAC#CLIENTTXACK to comply with inter-packet gap requirements and flow control requests. TEMAC User Guide www.xilinx.com 55 UG194 (v1.10) February 14, 2011
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Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13 and 14: R Additional Support Resources User
Page 15 and 16: R Typographical Online Document Use
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53: R Normal Frame Transmission CLIENTE
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 65 and 66: R Frame Reception with Errors CLIEN
Page 67 and 68: R Receive (RX) Client: 8-Bit Interf
Page 69 and 70: R Receive (RX) Client: 16-Bit Inter
Page 71 and 72: R Address Filtering Address Filteri
Page 73 and 74: R CLIENTEMAC#RXCLIENTCLKIN Flow Con
Page 75 and 76: R Transmitting a PAUSE Control Fram
Page 77 and 78: R Operation Figure 3-30 illustrates
Page 79 and 80: R Ethernet MAC Block EMAC#CLIENTTXS
Page 81 and 82: R Table 3-3: Bit Definitions for th
Page 83 and 84: R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
Page 85 and 86: R Host/DCR Bus Interfaces This chap
Page 87 and 88: HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
Page 89 and 90: R Table 4-3: Receiver Configuration
Page 91 and 92: R Table 4-5: Flow Control Configura
Page 93 and 94: R Table 4-7: RGMII/SGMII Configurat
Page 95 and 96: R Table 4-9: Unicast Address (Word
Page 97 and 98: R Table 4-13: Address Filter Mode 0
Page 99 and 100: R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
Page 101 and 102: R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
Page 103 and 104: R Using the DCR Bus The directly ad
Page 105 and 106:
R Table 4-18: DCR Control Register
Page 107 and 108:
R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114:
R Using the DCR Bus // EMAC Managem
Page 115 and 116:
R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
Page 119 and 120:
R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
Page 139 and 140:
R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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Page 151 and 152:
Page 153 and 154:
R Reduced Gigabit Media Independent
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Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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Page 163 and 164:
Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
Page 189 and 190:
R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
Page 211 and 212:
R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
Page 221 and 222:
R Additional Attributes Table C-2:
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R Appendix D Differences between So
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