Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Chapter 6: Physical Interface 1000BASE-X PCS/PMA Generic Host Bus DCR Bus Ethernet MAC PCS/PMA Sublayer Flow Control Interface Host Interface DCR Bridge Figure 6-18 shows the functional block diagram of the Ethernet MAC with the PCS/PMA sublayer block highlighted. EMAC# TX RX 16- or 8-Bit Client Interface Transmit Engine Flow Control Receive Engine Address Filter Registers MDIO Interface MAC Configuration Registers Figure 6-18: Functional Block Diagram of the Ethernet MAC The PCS/PMA sublayer extends the functionality of the Ethernet MAC, replacing the GMII/MII or RGMII parallel interfaces with an interface to a RocketIO serial transceiver. The connected RocketIO serial transceiver then provides the remaining functionality to accommodate the following two standards, both of which require the high-speed serial interface provided by the RocketIO serial transceiver: “Serial Gigabit Media Independent Interface (SGMII)” “1000BASE-X PCS/PMA” TX RX Statistics Clock Management Introduction to the 1000BASE-X PCS/PMA Implementation MII/GMII/RGMII Interface to External PHY GTP/GTX Transceiver Interface MDIO Interface to External PHY UG194_6_18_071709 The 1000BASE-X physical standard, described in IEEE 802.3, clauses 36 and 37, defines a physical sublayer that is usually connected to an optical fibre medium. Two common implementations currently exist: 1000BASE-LX and 1000BASE-SX (long and short wavelength laser), which can both be obtained by connecting the RocketIO serial transceiver to a suitable GBIC or SFP optical transceiver. 164 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 MII/GMII/RGMII Interface TX RX TX RX PCS/PMA Sublayer PCS Management Registers MDIO Intersection R
FPGA R PCS/PMA Sublayer MAC TX Interface MAC RX Interface MDIO Interface 1000BASE-X PCS/PMA Figure 6-19 shows an expanded diagram of the PCS/PMA sublayer block. The PCS/PMA sublayer contains its own functional blocks, which are illustrated and summarized in the following subsections. The RocketIO serial transceiver is shown connected to an external optical transceiver to complete the 1000BASE-X optical link. Figure 6-19: Ethernet PCS/PMA Sublayer Extension PCS Transmit Engine PCS Transmit Engine Auto-Negotiation PCS Receive Engine and Synchronization PCS Management Registers The PCS Transmit Engine encodes the datastream received from the MAC into a sequence of ordered sets as defined by the standard. The data is transmitted to the RocketIO serial transceiver using an 8-bit datapath that then provides 8B/10B encoding of this data and parallel to serial conversion. The output from the RocketIO serial transceiver is a differential pair operating at a rate of 1.25 Gb/s. For more information on the PCS Transmit Engine, refer to the state diagrams of IEEE 802.3 (Figures 36-5 and 36-6). PCS Receive Engine and Synchronization The RocketIO serial transceiver receives a serial differential pair operating at a rate of 1.25 Gb/s from the optical transceiver. The RocketIO serial transceiver, using CDR, performs word alignment on this serial datastream and then converts this to a parallel interface. This data is then 8B/10B decoded by the RocketIO serial transceiver before presenting this to the PCS/PMA sublayer using an 8-bit datapath. Within the PCS/PMA sublayer, the synchronization process performs analysis of valid/invalid received sequence ordered sets to determine if the link is in good order. The PCS receive engine then decodes these sequence ordered sets into a format that can then be presented to the standard receiver datapath within the Ethernet MAC. TEMAC User Guide www.xilinx.com 165 UG194 (v1.10) February 14, 2011 GTP/GTX Serial Transceiver TX+ TX- RX+ RX- GBIC or SFP Optical Transceiver PHY Link TX Optical Fiber RX UG194_6_19_00084089
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Virtex-5 FPGA Embedded Tri-Mode Eth
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Date Version Revision 08/08/07 (con
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Date Version Revision 10/01/09 1.9
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Table of Contents Guide Contents .
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R Chapter 5: MDIO Interface Introdu
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R About This Guide Guide Contents P
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R Additional Support Resources User
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R Typographical Online Document Use
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Introduction Key Features R Chapter
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R Typical Ethernet Application Over
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R Number of Bytes Physical Sublayer
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R Data Pad FCS Ethernet Protocol Ov
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R Using the Embedded Ethernet MAC T
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R Ethernet MAC Overview Chapter 2 T
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Generic Host Bus DCR Bus R Flow Con
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R Ethernet MAC Primitive Ethernet M
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R Ethernet MAC Signal Descriptions
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R Table 2-3: Receive Client Interfa
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R DCR Bus Signals Table 2-6: DCR Bu
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R Table 2-8: PHY Data and Control S
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R Table 2-12: PCS/PMA Signals Table
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R Table 2-16: Mode Configuration At
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R Table 2-17: MAC Configuration Att
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R Table 2-17: MAC Configuration Att
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R Table 2-18: Physical Interface At
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R Client Interface Chapter 3 This c
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R Normal Frame Transmission CLIENTE
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
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R Normal Frame Transmission PHYEMAC
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114: R Using the DCR Bus // EMAC Managem
Page 115 and 116: R MDIO Interface Chapter 5 This cha
Page 117 and 118: MDC MDIO R MDIO Transactions Introd
Page 119 and 120: R MDIO Implementation in the Ethern
Page 121 and 122: Generic Host Bus DCR Bus R PHYEMAC#
Page 123 and 124: R 1000BASE-X PCS/PMA Management Reg
Page 125 and 126: R Table 5-4: Status Register (Regis
Page 127 and 128: R 1000BASE-X PCS/PMA Management Reg
Page 129 and 130: R Table 5-13: Vendor-Specific Regis
Page 131 and 132: R 2, 3 “PHY Identifier (Registers
Page 133 and 134: 1.2 SGMII Link Status R Table 5-16:
Page 135 and 136: R Table 5-22: SGMII Auto-Negotiatio
Page 137 and 138: R Physical Interface Chapter 6 This
Page 139 and 140: R GMII / MII RGMII SGMII Introducti
Page 141 and 142: TX CLIENT LOGIC RX CLIENT LOGIC R M
Page 143 and 144: R Gigabit Media Independent Interfa
Page 145 and 146: GTX_CLK R IBUFG TX CLIENT LOGIC RX
Page 147 and 148: GTX_CLK R IBUFG BUFG TX Client Logi
Page 153 and 154: R Reduced Gigabit Media Independent
Page 157 and 158: GTX_CLK TX Client Logic RX Client L
Page 159 and 160: GTX_CLK TX Client Logic RX Client L
Page 163: R Reduced Gigabit Media Independent
Page 167 and 168: R Ethernet MAC to RocketIO Serial T
Page 169 and 170: TX and RX Client Logic R 1000BASE-X
Page 171 and 172: R 1000BASE-X PCS/PMA REFCLKOUT outp
Page 173 and 174: R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
Page 175 and 176: R 1000BASE-X PCS/PMA IEEE Std 802.3
Page 177 and 178: R 1000BASE-X PCS/PMA Ethernet MAC.
Page 179 and 180: FPGA R Introduction to the SGMII Im
Page 181 and 182: R RX Elastic Buffer Implementations
Page 183 and 184: R Serial Gigabit Media Independent
Page 189 and 190: R Ethernet MAC (PCS/PMA Sublayer) E
Page 191 and 192: TX and RX Client Logic R SGMII Cloc
Page 195 and 196: DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
Page 199 and 200: R Interfacing to a Statistics Block
Page 201 and 202: R Using the DCR Bus to Access Stati
Page 203 and 204: R Pinout Guidelines Appendix A Xili
Page 205 and 206: R Ethernet MAC Clocks Appendix B Th
Page 207 and 208: TX Client Logic RX Client Logic R
Page 209 and 210: R Clock Enables Clock Connections t
Page 211 and 212: R Receiver Clock Clock Definitions
Page 213 and 214: R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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