Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

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Preface: About This Guide Table 1-1: Acronyms and Abbreviations in this User Guide Acronym Definition IOB Input/Output Block ISE Xilinx Integrated Software Environment L/T Length/Type field (MAC frame) LAN Local Area Network MAC Media Access Controller Mb/s Megabits per second MDIO Management Data Input/Output MII Media Independent Interface OP Operation code (read or write) for MDIO frame (sometimes called OPCODE in text) OSI Open Systems Interconnection PCB Printed Circuit Board PCS Physical Coding Sublayer PHY Physical Layer The term refers to all physical sublayers (PCS, PMA, PMD). Often applied to a device, e.g., BASE-T PHY: an external chip which can connect to the Ethernet MAC to perform this physical standard PHYAD Physical Address (MDIO Frame) PLB Processor Local Bus PMA Physical Medium Attachment PMD Physical Medium Dependent PRE Preamble (MDIO Frame) REGAD Register Address (MDIO Frame) RGMII Reduced Gigabit Media Independent Interface RX Receiver SA Source Address (MAC frame) SFD Start of Frame Delimiter (MAC frame) SFP Small Form-factor Pluggable (optical transceiver) SGMII Serial Gigabit Media Independent Interface ST Start Code (MDIO Frame) or Start of Frame Stats Abbreviation of Statistics TA Turnaround (MDIO Frame) TX Transmitter VLAN Virtual Local Area Network 14 www.xilinx.com TEMAC User Guide UG194 (v1.10) February 14, 2011 R
R Typographical Online Document User Guide Conventions This document uses the following typographical conventions. An example illustrates each convention. Convention Meaning or Use Example Italic font References to other documents Emphasis in text The following conventions are used in this document: See the Virtex-5 User Guide for more information. The address (F) is asserted after clock event 2. Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex5 Blue text Convention Meaning or Use Example Cross-reference link to a location in the current document Blue, underlined text Hyperlink to a website (URL) See the section “Additional Documentation” for details. Refer to “Address Filtering” in Chapter 3 for details. Go to http://www.xilinx.com for the latest documentation. TEMAC User Guide www.xilinx.com 15 UG194 (v1.10) February 14, 2011
Page 1 and 2: Virtex-5 FPGA Embedded Tri-Mode Eth
Page 3 and 4: Date Version Revision 08/08/07 (con
Page 5 and 6: Date Version Revision 10/01/09 1.9
Page 7 and 8: Table of Contents Guide Contents .
Page 9 and 10: R Chapter 5: MDIO Interface Introdu
Page 11 and 12: R About This Guide Guide Contents P
Page 13: R Additional Support Resources User
Page 17 and 18: Introduction Key Features R Chapter
Page 19 and 20: R Typical Ethernet Application Over
Page 21 and 22: R Number of Bytes Physical Sublayer
Page 23 and 24: R Data Pad FCS Ethernet Protocol Ov
Page 25 and 26: R Using the Embedded Ethernet MAC T
Page 27 and 28: R Ethernet MAC Overview Chapter 2 T
Page 29 and 30: Generic Host Bus DCR Bus R Flow Con
Page 31 and 32: R Ethernet MAC Primitive Ethernet M
Page 33 and 34: R Ethernet MAC Signal Descriptions
Page 35 and 36: R Table 2-3: Receive Client Interfa
Page 37 and 38: R DCR Bus Signals Table 2-6: DCR Bu
Page 39 and 40: R Table 2-8: PHY Data and Control S
Page 41 and 42: R Table 2-12: PCS/PMA Signals Table
Page 43 and 44: R Table 2-16: Mode Configuration At
Page 45 and 46: R Table 2-17: MAC Configuration Att
Page 47 and 48: R Table 2-17: MAC Configuration Att
Page 49 and 50: R Table 2-18: Physical Interface At
Page 51 and 52: R Client Interface Chapter 3 This c
Page 53 and 54: R Normal Frame Transmission CLIENTE
Page 55 and 56: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 57 and 58: R CLIENTEMAC#TXCLIENTCLKIN CLIENTEM
Page 59 and 60: R Normal Frame Transmission PHYEMAC
Page 61 and 62: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
Page 63 and 64: R CLIENTEMAC#TXCLIENTCLKIN PHYEMAC#
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R Frame Reception with Errors CLIEN
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R Receive (RX) Client: 8-Bit Interf
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R Receive (RX) Client: 16-Bit Inter
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R Address Filtering Address Filteri
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R CLIENTEMAC#RXCLIENTCLKIN Flow Con
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R Transmitting a PAUSE Control Fram
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R Operation Figure 3-30 illustrates
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R Ethernet MAC Block EMAC#CLIENTTXS
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R Table 3-3: Bit Definitions for th
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R CLIENTEMAC#RXCLIENTCLKIN EMAC#CLI
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R Host/DCR Bus Interfaces This chap
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HOSTCLK HOSTMIIMSEL HOSTREQ HOSTOPC
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R Table 4-3: Receiver Configuration
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R Table 4-5: Flow Control Configura
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R Table 4-7: RGMII/SGMII Configurat
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R Table 4-9: Unicast Address (Word
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R Table 4-13: Address Filter Mode 0
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R HOSTCLK HOSTMIIMSEL HOSTOPCODE[1]
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R HOSTCLK HOSTMIIMSEL HOSTREQ HOSTO
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R Using the DCR Bus The directly ad
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R Table 4-18: DCR Control Register
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R Using the DCR Bus The IRENABLE_e#
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R // Write to the cntlReg_e1 regist
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DCR Offset 0x1 MSB R Using the DCR
Page 113 and 114:
R Using the DCR Bus // EMAC Managem
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R MDIO Interface Chapter 5 This cha
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MDC MDIO R MDIO Transactions Introd
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R MDIO Implementation in the Ethern
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Generic Host Bus DCR Bus R PHYEMAC#
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-4: Status Register (Regis
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R 1000BASE-X PCS/PMA Management Reg
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R Table 5-13: Vendor-Specific Regis
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R 2, 3 “PHY Identifier (Registers
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1.2 SGMII Link Status R Table 5-16:
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R Table 5-22: SGMII Auto-Negotiatio
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R Physical Interface Chapter 6 This
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R GMII / MII RGMII SGMII Introducti
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TX CLIENT LOGIC RX CLIENT LOGIC R M
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R Gigabit Media Independent Interfa
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GTX_CLK R IBUFG TX CLIENT LOGIC RX
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GTX_CLK R IBUFG BUFG TX Client Logi
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Page 151 and 152:
Page 153 and 154:
R Reduced Gigabit Media Independent
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Page 157 and 158:
GTX_CLK TX Client Logic RX Client L
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GTX_CLK TX Client Logic RX Client L
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Page 163 and 164:
Page 165 and 166:
FPGA R PCS/PMA Sublayer MAC TX Inte
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R Ethernet MAC to RocketIO Serial T
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TX and RX Client Logic R 1000BASE-X
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R 1000BASE-X PCS/PMA REFCLKOUT outp
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R DCM BUFG CLKFB CLK0 CLKIN CLKFX B
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R 1000BASE-X PCS/PMA IEEE Std 802.3
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R 1000BASE-X PCS/PMA Ethernet MAC.
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FPGA R Introduction to the SGMII Im
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R RX Elastic Buffer Implementations
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R Serial Gigabit Media Independent
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Page 187 and 188:
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R Ethernet MAC (PCS/PMA Sublayer) E
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TX and RX Client Logic R SGMII Cloc
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Page 195 and 196:
DCM CLKFB CLK0 CLKIN CLKDV CLKDV_DI
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Page 199 and 200:
R Interfacing to a Statistics Block
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R Using the DCR Bus to Access Stati
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R Pinout Guidelines Appendix A Xili
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R Ethernet MAC Clocks Appendix B Th
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TX Client Logic RX Client Logic R
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R Clock Enables Clock Connections t
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R Receiver Clock Clock Definitions
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R GMII (Byte PHY) Mode Clock Defini
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R Clock Definitions and Frequencies
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R Virtex-4 to Virtex-5 FPGA Enhance
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R Clock Enables Modifications Relat
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R Additional Attributes Table C-2:
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R Appendix D Differences between So
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