Xilinx UG194 Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC ...

Appendix B: Ethernet MAC Clocks
Receiver Client Clock
EMAC#CLIENTRXCLIENTCLKOUT can be placed onto global clock routing and used to
clock all of the receiver client logic. This resultant clock is then fed back into the Ethernet
MAC on the CLIENTEMAC#RXCLIENTCLKIN, where it is used to derive the internal clock
used for the receiver client datapath. This configuration has the effect of eliminating clock
skew between the Ethernet MAC and the FPGA logic (caused by the global clock routing),
enabling data to be reliably transferred between the two.
Transmitter Physical Clock
EMAC#PHYTXGMIIMIICLKOUT can be placed onto global clock routing and used to clock
all of the transmitter physical logic. This resultant clock is then fed back into the Ethernet
MAC on the PHYEMAC#TXGMIIMIICLKIN, where it is used to derive the internal clock
used for the transmitter physical datapath. This configuration has the effect of eliminating
clock skew between the Ethernet MAC and the FPGA logic (caused by the global clock
routing), enabling data to be reliably transferred between the two.
Receiver Physical Clock
The physical clock for the receiver interface is sourced by the connected PHY. When placed
onto global clock routing, this resultant clock is also fed into the Ethernet MAC on the
PHYEMAC#RXCLK port and is used to derive the internal clock used for the receiver
physical datapath. This enables data to be reliably transferred from the FPGA logic into the
Ethernet MAC.
Advanced Clocking Schemes
Two advanced clocking schemes are developed for the Virtex-5 FPGA Ethernet MAC. Both
of these clocking schemes reduce the global clock usage in the FPGA logic.
“Clock Enables” evolved from an FPGA logic enhancement for the Virtex-4 FPGA
Ethernet MAC. The Virtex-4 FPGA clock enable signals were created in the FPGA
logic, resulting in a clocking scheme that halved the global clock usage when using
the MII physical interface for 10 Mb/s or 100 Mb/s.
The Virtex-5 FPGA clock enables are provided by the Ethernet MAC to the FPGA logic,
and their use extends to cover MII, GMII, and RGMII interfaces at all three Ethernet
speeds.
“Byte PHY” also evolved from an FPGA logic enhancement for the Virtex-4 FPGA
Ethernet MAC and provided a solution that halved the global clock usage when using
the GMII/MII physical interface at all three speeds. However, it supported only fullduplex
mode.
In Virtex-5 devices, the Byte PHY functionality extends to cover the GMII/MII, at all
three speeds, supporting both full- and half-duplex modes.
Clock Enables and Byte PHY advanced clocking modes are offered by the
CORE Generator tool for both the Virtex-4 and Virtex-5 FPGA Ethernet MACs.
However, as previously described, these options are available for the Virtex-5 FPGA
Ethernet MAC over a wider range of configurations.
208 www.xilinx.com TEMAC User Guide
UG194 (v1.10) February 14, 2011
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