ETTC'2003 - SEE

BpNet has been extensively used for the
first time in the IENA modeling phase.
Very recently, a complex Radar
application has successfully used BpNet to
build an image processing system (pipeline
structure), traditionally implemented with
DSPs, on a set of CES RIOCs (CPCI PPC
7410 SBCs).
The vmeQuick package originated from
the need to handle the hardware address
translation between onboard and backplane
bus (VME) addresses in an efficient and
portable way. This need became first
apparent in the AIDASS military aircraft
test system, which requires a large VME
address space that exceeds the size of the
VME window of a SBC. Later the system
evolved to integrate the use of DMA
mechanisms wherever possible. This is
transparent to the application, which can
be written to run without modification on a
system providing hardware DMA support
and a system that does not. The vmeQuick
package will use the hardware DMA if
available and will otherwise emulate this
function.
Air/Ground
The first generation of CES PPC based
SBCs and PMCs, the RIO2 8062 and
MFCC 8441 and 8442 had been designed
using exclusively commercial grade
components. But even without special
precautions on the board level, it turned
out that function units built with these
boards could be used in air-borne as well
as in ground based systems. The
requirements of the air-borne environment
could be met by the design of an
appropriate chassis.
Soon after the introduction of the second
generation of CES PPC boards, CES has
been asked to design a version of the
RIO3 8064 that is 100% software
compatible to the ‘standard’ model, but
capable to serve in a system meeting the
requirements of the Aircraft Ground
Equipment (AGE) specification. The
resulting SBC, the RIO3E (E for extended
specs) is today one of the basic elements in
the IENA-N2-AFDX concentrator system.
As mentioned above, this system also
builds on the experience gained by the
AGE chassis development, which was at
the trigger of the RIO3E design in the first
place.
The RIO3E also fitted the requirements of
the Predator program evolution. However,
the next step in this program involves
flight altitudes that require conduction-
cooled equipment. CES has developed a
conduction-cooled variant of the RIO3, the
RIO3 8066, which is again software
compatible to the other members of the
RIO3 family.
Today, the availability of components in
both commercial and industrial grade is
part of the basic design rules for the next
generation of CES processor boards. This
generation will be designed from the start
to be available in standard, extended-specs
and conduction-cooled variants.
Chassis
Environmental specifications rarely apply
to individual boards. It is always the
system that must fulfill the requirements.
For this reason the design of an appropriate
chassis is crucial when designing systems
that have to meet ambitious environmental
specifications. Even in the laboratory
environment, few commercially available
chassis are well adapted to systems that
assemble a high number of powerful CPUs
in relatively few slots. CES has, in
collaboration with chassis manufacturers,
developed a series of chassis that allow to
rapidly build reliable multi-processor
systems. A particularly ambitious example
is the chassis used in the IENA-N2-AFDX
concentrator. It is available in an air-borne
and a laboratory version. This chassis is