ETTC'2003 - SEE

shown below together with the AGE
chassis from which it was developed.
Figure 1: IENA-N2-AFDX concentrator (Lab
version)
Figure 2: AGE chassis (EADS Military Aircraft)
Datation
Data acquired by a complex aircraft test
system can only be analyzed if data
originating from different instruments
(parameters) can be precisely correlated in
time. The IENA system requires global
datation (time-stamping) of all acquired
parameters with a 0.5 microsecond
precision and a 1 microsecond 48-bit wide
resolution for long-term applications. The
system must be synchronized with an
external GPS time source in order to be
able to correlate data acquired by
independent test systems.
During the IENA modeling phase, CES
developed a global synchronization system
meeting these requirements. This system
was first used for time-stamping PCM data
acquired by the MFCC 8441 based
PCM 5367 function unit. An enhanced
version of this system, which allows direct
IRIG-B input into the datation master unit
(DAT 5384), is part of the IENA-N2
AFDX concentrator.
Independently, the AIDASS system uses a
system wide time-stamping mechanism
with 10 microseconds precision, but
without direct GPS synchronization (timestamp
counters start counting from zero
after system reset). With the integration of
the AFDX general test resource into
AIDASS both time-stamping methods will
be supported b y the system. Since this
function is implemented in the application
specific FPGA of the MFCC, it is also
feasible to directly integrate the IENAstyle
datation method into a variant of the
MIL 1553 and EFABUS function unit.
For the next generation of CES PPC SBCs
(RIO4, s. below), the integration of a GPS
receiver directly on board (no PMC), as
well as an on board solid state disk is
foreseen.
Next generation
By the end of 2003, CES plans to have the
first units of its new generation of boards
operational. All boards in this family will
use Xilinks Virtex II Pro FPGAs in which
part of the available logic is reserved for
application specific developments. The
remaining FPGA resources will be used to
implement powerful bus interfaces (e.g.
VME 2eSST) and a sophisticated monitor
and control system which allows to subdivede
a system composed of SBCs and
PMCs into secure cells, functional
subunits which can be individually reconfigured
and re-started without the need
for a global system reset. The new family
consists of
• The RIO4 8070, a VME SBC with
up to two PPC 7457 CPUs, up to
2 GBytes of main memory, 10-