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ETTC'2003 - SEE

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Binary X<br />

Binary to RNS and RNS to Binary dataflow<br />

Binary<br />

to<br />

RNS<br />

Conversion<br />

RNS Processor<br />

RNS Processor<br />

RNS Processor<br />

DSP Algorithm<br />

Binary<br />

to<br />

RNS<br />

Conversion<br />

CRT/MRC<br />

output Y<br />

1.1.4. Conclusion<br />

1. RNS is an integer system<br />

2. Addition, subtraction and multiplication are fast<br />

3. Division is a complex process but certain stipulations are defined which allow for the<br />

inverse of a number to exist.<br />

4. RNS is not a weighted number system which means that magnitude comparison, sign<br />

detection and overflow detections properties are not embedded. One needs to use<br />

MRC for implementation.<br />

1.2. Reconfigurable embedded cores<br />

IF<br />

FrontEnd<br />

The object of the current program is to develop embedded cores based on RNS for<br />

system level applications. In order to evaluate the performance, the Digital Down<br />

Converter (DDC) has been selected. The digital down converter is made of three<br />

cores, a NCO (Numerical Control Oscillator), a mixer and decimation filters. The<br />

NCO provides a small frequency resolution with fast frequency switching. The<br />

conceptual view of the DDC is given below:<br />

ADC<br />

L<br />

X<br />

X<br />

Phase Accumulator<br />

L<br />

Reg<br />

AGC<br />

and<br />

CIC<br />

W<br />

NCO<br />

ROM<br />

AGC<br />

and<br />

CIC<br />

AGC<br />

and<br />

CIC<br />

AGC<br />

and<br />

CIC<br />

I<br />

FI<br />

R<br />

Q

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