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ETTC'2003 - SEE

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The index multiplier block will be evaluated in an FPGA logic block as well as in the<br />

RAM block.<br />

Decimation Filters<br />

In a two’s complementary based decimation filter, the required word length may vary<br />

between 40 and 56 bits. It depends on the decimation factor and the bandwidth<br />

n n n−1 n−2<br />

characteristics. In our evaluation, the selected moduli type is 2,2−1,2−1,2− 1<br />

and n will vary between 11 and 15. As the dynamic range changes from application to<br />

application, a software RNS calculator is developed. A part of the calculator display<br />

is given below.

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