ETTC'2003 - SEE

The current implementation consists of three parts: NCO, mixer and decimation filters
which are evaluated separately using RNS based numerical processing before
integration into a Digital Down Converter on FPGA from Altera and Xilinx for
performance evaluation in the logic and memory block utilization.
References
[1] S. K. Mitra, J. F. Kaiser,”Handbook for Digital Signal Processing,”.
[2] Computer Arithmetic, Algorithms and Hardware Design by B.Parhami, Oxford university press.
[3] P.V Ananda Mohan, “ The digital Parallel method for fast RNS to weight number system conversion for specific moduli
(
k− 1 k k+
1
IEEE Trans. On circuits and systems, Part-II,Vol.47, 2000.
2 ,2 ,2 )",
[4] A.Z.Baraniecka and G.A. Jullien, Residue Number System Implementations of Number Theoretic Transforms
in Complex Residue Rings, IEEE Trans ASSP 28 ,1980.
[5] N.S Szabo and R..I Tanaka, Residue Arithmetic and Its Applications to computer technology, Mc-Graw Hill,
1967.
[6]A.P. Shenoy and Kumaresan. Fast base extension using a redundant modulus in RNS. IEEE Transactions on
Computers, 382, 1989.
[7]. W.A. Chren, Jr., “ RNS- base enhancements for direct digital synthesis,” IEEE Trans. Circuits Syst II, vol. 42,
1995.
[8] G.A Jullien “ Implementation of multiplications, modulo a prime numbers with applications to Number
Theoretic Transforms” IEEE Trans. On computers, vol 29, 1980.
[9] D. Radhakrishnan and Y. Yuan, “ Novel Approaches to the Design of VLSI RNS Multipliers”, IEEE Trans. On
Circuit and Systems-II: Analog and Digital Signal Processing, vol. 39, 1992.
[10] D.Radhakrishnan and A.P. Preethy, Noval Galois Field Techniques for a 32 bit Superset Modulo Multiplier, Nanyang
Technical University.