Online proceedings - EDA Publishing Association

11-13
May 2011, Aix-en-Provence, France
D. Guidelines and design rules for 90 nm CMOS-MEMS
III. SYSTEM TEST DESIGNS
Table I shows typical process parameters for the dielectric
etch using a Plasma-Therm 790 parallel-plate RIE system.
As the dielectric etch step is the most challenging step, the
other two etch steps remain the same. For this run the etch
time was slightly longer compared to a coarse-grain post-
CMOS run, and at the end of the process O2 rinsing of the
dies were performed.
TABLE I
Post-process dielectric etch step
Typical
20 CHF3
Gas flow [sccm] 20 CF4
95 O2
Pressure [mT] 100
Power [W] 65
DC bias [V] 270
Time [min] ~120
General observations:
• Beams curling sideways, upwards and even downwards
were observed
• Structures that are long and have sufficiently small widths
will delaminate and start to curl before the release-etch
• Creating uniform spacing in the MEMS area will reduce
the sideways curling phenomenon greatly
• Homogenous material stacks curled less
• Using the active layer will reduce curling
• The thickness of the top metal layer is slightly milled
• Polymer deposition on the sidewalls was negligible
• The top metal layer had clearly defined edges
TABLE II
Tentative 90 nm post-CMOS design rules
Dim. [!m] Rule name Comment
Minimum width 1 W1 Delamination
Maximum width ~10 W2 CMOS rule
Max length fixed-free < 60 L1 Delamination
Max length fixed-fixed < 100 L2 Curling
Max stack thickness ~5 H1 Preliminary
Gap spacing 1.2 S1 Guarantees release
Poly from metal edge 0.6 S2 Prone to etch
Active cover edge 0.3 A1 Reduce curling
Active sep poly ~0.1 A2 CMOS rule
Table II shows general design rules and guidelines for a
general purpose 90 nm CMOS process.
General purpose 90 nm post-CMOS summary:
Pros
• Possible smaller electrostatic gaps
• Less parasitics
• Lower supply voltage for less power consumption
• More intricate routing capabilities
• More in thread with newer CMOS processes
Cons
• Smaller stack thickness possible
• More stringent CMOS design rules, especially the
density rules in the MEMS areas
• Curling and delamination more prominent
In this work, a set of soft-tunable MEMS resonators to be
used as voltage-controlled oscillators (VCO) have been
implemented. Fig. 10 shows an electromechanical equivalent
schematic of the MEMS resonator with the previously
described electromechanical coupling coefficient ". The lz, cz
and rz are related to mechanical and electrical parameters of
the resonator. A signal at the resonance of the resonator
results in the lz and cz reactances becoming equal but with
opposite sign, thus the only part left is the damping part of
the resonator which is rz. When tuning the resonance
frequency with VP, the lz and cz changes values. CP is a
parasitic element from the routing of the MEMS resonator to
the following amplifier.
Fig. 10. Electromechanical schematic representation of the resonator
A soft tunable parallel-plate tuning fork (PPTF) with selfassembly
beams is shown in fig. 11. The part of the
resonator that overlaps the fixed electrodes will have equal
displacement throughout the electrode length in order to
reduce non-linearities. The left part of fig. 11 shows how the
electrostatic gaps are reduced by using self-assembly (SA)
electrodes. The beams are designed to have more metal
layers on one side for each half of the SA length. A lateral
force internally is generated due to built-in sideways stress
during processing, and the SA will move after release and
create a 200 nm small gap between the resonator and the
electrode.
SA (in) PPTF SA (out)
1.2 m
0.6 m
1.2 m
VAC
0.6 m
1 : !
Out
Out
lz cz rz ! : 1
Fig. 11. Left: The self-assembly concept. Right: PPTF-resonator with SA
The lateral displacement of a self-assembly beam is shown
more clearly in fig. 12 where the self-assembly beams are
100 !m long and 2 !m wide. Another MEMS resonator
design with self-assembly beams was implemented as a
clamped-clamped (CC) beam as shown in fig 13.
CP
+
-
119