Online proceedings - EDA Publishing Association

11-13
May, 2011, Aix-en-Provence, France
Fabrication of High Aspect Ratio Nanoporous Array
on Silicon
Jing-Yu Ho 1 1, 2*
and Gou-Jen Wang 1 Department of Mechanical Engineering
2 Graduate Institute of Biomedical Engineering
National Chung-Hsing University, Taichung 40227, Taiwan
Tel:+886-4-22840725 x 320
Email: gjwang@dragon.nchu.edu.tw
Abstract- In this study, a simple method for the fabrication of high
aspect ratio silicon nanoporous arrays is developed. A N-type
silicon wafer is used as the material; a micro-scale pattern of the
desired porous array is transferred to the front surface of the
silicon wafer by photolithography; the wafer is placed in a
home-made fixture to efficiently expel the etching generated air
and promptly hold the back-side illumination light; a halogen
lamp is used as the light source for backside illumination to
enhance the electron-hole pairs generation; anodization is then
processed using a new etchant which consists of the hydrofluoric
acid and the EtOH and EMSO mixed surfactant to effectively
polish the pore surface and sharp the tips of the etched pores. A
nanochannel array with nano-tip being 61.4 nm is obtained.
I. INTRODUCTION
Porous silicon has attracted increasing interest owing to the
advantages such as easily being fabricated in large area, pores
being able to be arranged in order and patterned, and pores’
shape being able to be adjusted by the process parameters. In
addition, the semiconducting characteristic enables a porous
silicon device to reveal different physical and/or chemical
properties due to variation of porosity. Porous silicon can be
found variety applications in light emitting diode (LED) [1],
photodetector [2], solar cell [3], photonic crystal, photo sensor
[4], biosensor [5], and field emission display [6].
It has been nearly 50 years since the invention of porous
silicon. However, the formation mechanism of porous silicon is
still being developed. Parkhutik et al. [7] proposed that the
relatively thinner oxide layer between the pores and the
substrate enhances the electric field at each pore end; hence the
silicon atom can easily acquire electric hole then dissolves. A
high aspect ratio structure can thus be obtained. The basic
principle is similar to that of the anodic aluminum oxide.
Unagami [8] proposed that the porous silicon layer (PSL) is
constructed by the local dissolution of silicon which happens
only at the base of the pores. The divalent and the tetravalent
reactions of silicon with hydrofluoric acid (HF) are the main
driving forces for the dissolution of silicon in the pores.
Theunissen et al. [9] reported that at the tip of a pore in N-type
material, silicon atoms are likely to reach the breakdown
voltage then dissolve due to the concentration of electric field.
Beale [10] suggested that the depletion layer influences the
distribution of the electric field in the silicon substrate, hence
affects the porous structure. Smith et al. [11] proposed that the
diffusion of the electric holes toward the interface between the
silicon material and the etching solution determines the etching
process. Lehmann et al. [12] pointed out that the band gap of
the whole system is increased after the growth of the porous
silicon such that the charge concentration in the porous silicon
is reduced. A high aspect ratio pore array thus can be produced.
Several factors affect the structure of a silicon porous array.
Rönnebeck et al. [13] investigated the etching behavior in
N-type and P-type materials. It was pointed out that the degree
of doping in silicon substrate influences the etching results
since it determines the thickness of the depletion layer.
Carstensen et al. [14] compared the effects of HF concentration,
different surfactants, and illumination intensity. Tsuboi et al.
[15] studied the influences of the applied field induced
polarization of the surfactant on the etching results. Among
those reported studies, the size of the pores ranges from
submicron to several micron. For delicate applications such as
the detection of DNA sequences, nano-scale pores are desired.
In this study, a simple process for the fabrication of
nano-size silicon porous array is proposed. A N-type silicon
wafer is used as the material; a micro-scale pattern of the
desired porous array is transferred to the front surface of the
silicon wafer by photolithography; the wafer is placed in a
home-made fixture; the anodization is then processed using HF
as the etching solution mixed with two surfactants to smoothen
the etched surface under backside illumination.
2.1 Materials
II.
MATERIALS AND METHODS
(1) N-type silicon wafer
As mentioned, diffusion of the electric holes plays an
important role in the etching process of silicon [11]. Since the
major carriers in P-type material are electric holes, the
dissolution rate of silicon in P-type material is higher than that
in N-type material. However, the etching process in P-type
material is difficult to be well controlled. Lateral etching is the
general problem. In this study, N-type material with thickness
and resistivity being 525 ± 25μm and 1~100Ω-cm 2 respectively
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