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B. First-order Σ-Δ ADC Design
The term of Σ-∆ ADC has become almost synonymous
with noise shaping ADC. Oversampling reduces the
quantization noise power in the signal bandwidth by
spreading the quantization noise power over a larger
frequency range [5]. Noise shaping attenuates this noise in
the signal bandwidth and amplifies it outside of the signal
bandwidth. A low-pass filter is used to attenuate the
out-of-band quantization noise. A down sampling circuit is
added to obtain the Nyquist rate output.
As shown in Fig.5, the first-order Σ-∆ ADC consists of a
discrete-time integrator, a 1-bit ADC (comparator), a D
flip-flop, and a 1-bit digital-to-analog converter (DAC) in the
feedback path. Here, the internal ADC and DAC are both low
resolution. Insertion of a buffer in series with a comparator is
done in order to make the D flip-flop work properly.
The analog signal processing circuit comprises of
switch-capacitor circuits [6]. In comparison with the
continuous time circuits consisting of resistors, capacitors
and op amp [7], this technique produces a more accurate
frequency response, good linearity and dynamic range. The
most important component which is displayed in Fig.6 is the
two-stage op amp. Table III describes the op amp design
specifications while Table IV summarizes the op amp
simulation results. The design of comparator is almost same
as the op amp, except there’s no compensation capacitor
between differential stage and inverter stage.
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May 2011, Aix-en-Provence, France
TABLE IV
THE OP AMP DESIGN RESULTS
Transistor M1 M2 M3 M4 M5 M6 M7 M8
(W/L) 36 36 6 6 39.38 39.6 107.8 78.77
Component I dc C c
Value 80μA 8pF
IV.
SIMULATION AND RESULTS ANALYSIS
A. MEMS Capacitive Sensor Simulation
The CMOS-MEMS differential capacitive sensor was
simulated using COMSOL Multiphysics ® , and the 3D model
is presented in Fig.7.
Equations (4) and (5) provide the relationship between the
distance changes (Δd) and the values of differential
capacitors; and the simulated results are shown in Fig.8. It
can be observed that the distance changes of within 1.5μm
causes the capacitance to change in hundredfold of fF. The
changing output voltage however, is linear to the sensing
displacement of as shown in Fig.9.
Fig.7. The CMOS-MEMS differential capacitive model in 3D.
Fig.6. The schematic of two-stage op amp.
Specification
TABLE III
THE OP AMP DESIGN SPECIFICATIONS
Power Band Phase
Supply Width Margin
Open
Loop Gain
Design Value ±1.2V 10kHz ≥75° ≥100
Input
Slew Settling
Specification Signal
Rate Time
Range
Minimum
Length of
Transistor
Design Value -0.7V~0.7V 4.45μs ≤1kΩ 130nm
Fig.8. Calculated and simulated results for the differential capacitive sensor.
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