Online proceedings - EDA Publishing Association

11-13
May 2011, Aix-en-Provence, France
FPGA
(XC3S50AN)
Connector for RF-
Transceiver
LED-Array
Fig. 5. Data path from the analog frontend to the transceiver for one
sample interval. In this example, the resolution was set to 9 Bit and the
channel mask is set to FFFF000000000000000000000000C003, which
means, that four channels of the first, and 16 channels of the last RHA
are transmitted while the remaining RHAs 1-6 are ignored [5].
commands into the according registers. In case of a new
channel mask, the measurement gets interrupted, and the
channel stack of the Protocol Builder is reprogrammed.
After the “measurement on” command, the Controller
checks if the transceiver is initialized and enables the
measurement sequence.
Register Bank: The registers store the values of the
command parameters which are also included in the
measurement data frame (Fig. 6): Channel_Mask[127:0],
RHA_Filter[3:0], Sample_Rate[7:0] and Resolution[3:0].
IV. RESULTS
A. FPGA Prototype
The FPGA prototype will serve as a development
platform on the way to higher integration. It allows us to
develop the software and test the compatibility with the
latest version of our digital system. Fig. 7 shows the FPGA
prototype without the transceiver board, which is normally
placed on top of the stack. The prototype provides the
smallest device of the Spartan3AN series, some simple
debug capability (pinheader and LEDs), a power supply (for
battery operation), sockets for the RHA modules, the
external filter components and connectors for attaching up
to 128 electrodes plus reference electrodes.
The prototype has a size of 5x5 cm² and a height of 3 cm.
The power consumption for the prototype with one
connected RHA is about 120 mW. The dynamic loss of the
digital core is below 200µW, which is the difference in
overall power consumption between a running measurement
and the digital core held in the reset state. The design
utilizes 363 Flip-flops and 693 LUTs.
Power supply
& crystal unit
Slots for
additional
RHAs
Fig. 7. FPGA prototype for functional verification.
RHA2216
assembled on
socket
B. Test System
For testing the prototype we use a National Instruments
PXI System with a FlexRIO card. This allows us to reuse
modules from the Simulation Testbench, which can be
implemented on the FPGAs of the FlexRIO card. The User
Interface (Fig. 8) was programmed using LabView and
allows to control all available functions of the system. Fig. 9
shows some qualitative measurement results from a sine
stimulus.
V. CONCLUSION
The programmable neuro frontend presented in this paper
covers nearly every conceivable application in neural
engineering or neural prostheses. Due to the high degree in
flexibility, one can easily shrink or expand the system
performance in order to fit the functional constraints defined
by the desired application.
Even if the constraints are partly unknown or unspecified,
one can use our system to evaluate and to determine the
needed performance in order to meet the objective target.
Fig. 6. Measurement Data Frame. Fig. 8. LabView Software for Controlling the Prototype [6].
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