Online proceedings - EDA Publishing Association

11-13
May 2011, Aix-en-Provence, France
Low Power Analog to Digital Convertor with Digital
Calibration for Sensor Network
Tsukasa Fujimori, Hiroshi Imamoto, Hideaki Kurata, Yasushi Goto, Toshihiro Ito, Ryutaro Maeda
BEANS Laboratory G device Center
G Device Research Body Ubiquitous MEMS and Micro Engineering R.C.
1-2-1, Namiki, Tsukuba, Ibaraki 305-8564, JAPAN
Abstract- A low-power analog-front-end (AFE) LSI for
sensor networks—based on an analog-to-digital convertor
(ADC) with digital calibration—was developed. Power
consumption of the ADC in the AFE LSI was reduced by
applying digital calibration. As a result, the proposed
successive approximation register (SAR) ADC achieves both
high effective resolution (11.7 bits) and extremely low power
consumption (2.5 mW) at 1 Msps. Moreover, average power
consumption of the AFE LSI (including the ADC) is about 5
μW, which is low enough for sensor networks.
I. INTRODUCTION
Energy-saving technologies for CO2 emission reduction
have become ever more important in recent years. Sensor
networks have been expected to provide one of the
most-promising solutions for energy saving. However, the
large physical size and high power consumption of sensor
nodes have been major constraints on the widespread usage of
sensor networks.
Sensor nodes generally consist of batteries, wireless circuits,
a microcomputer, sensors, and analog-front-end (AFE) circuits.
The wireless circuits and the microcomputer utilize
deep-submicron CMOS technology to reduce power
consumption. On the other hand, the power consumption of
the AFE circuits has not been reduced. It is not easy to apply
deep-submicron CMOS technology for the AFE circuits,
which include amplifiers and analog-to-digital converters
(ADCs), because the analog circuits that compose the AFE
circuits are sensitive to process variation. It is therefore
essential to develop low-power AFE circuits for sensor
networks.
Responding to the above-mentioned need, in the present
study, we developed a low-power AFE LSI for a sensor
network by utilizing an ADC with digital-calibration, which
are generally used for developing high speed and high
accuracy ADC circuits. Power consumption of the ADC in the
AFE circuits was reduced by applying digital-calibration
techniques. As a result, an ADC with high effective resolution
of 11.7 bits and extremely low power consumption of 2.5 mW
at 1 Msps (mega samples per second) was developed.
Moreover, average power consumption of the AFE LSI
(including the ADC) is about 5 μW, which is low enough for
sensor networks.
II. TARGET OF AFE LSI FOR SENSOR NETWORK
Figure 1 shows a block diagram of the AFE LSI, which
consists of an ADC, a programmable gain amplifier (PGA), a
voltage-reference (Vref) generator, a clock generator, and
digital interface circuits. The ADC is a successive
approximation register (SAR) type [2]. The AFE LSI
amplifies analog signals from the sensors and converts them
into digital signals. Note that most of the required periphery
circuits for these circuits are also built-in.
Table 1 lists the performance targets for the developed AFE
LSI. Resolution of the ADC of 14 bits, effective resolution of
ADC of 11 bits or more, and sampling rate of the ADC of 1
Msps all exceed the performance of the ADC generally used
by sensor nodes, and the target power consumption is below
10 mW (which is the approximate power consumption at the
time of operation). Furthermore, the target average power
consumption when performing one sampling per second is 10
μW or less. These power consumptions are one half or less
than those of present AFE circuits.
Sensor A
Sensor B
Sensor C
Sensor D
M
UX
M
UX
Digital interface circuits MCU
Figure 1.
PGA
Vref generator
SAR ADC with
digital calibration
Clock generator
Block diagram of AFE LSI
Table 1. Targets of the AFE LSI for sensor network
Targets
Resolution
14 bits
(effective resolution >11 bits)
Sample rate
1 Msps
Power (active)