Online proceedings - EDA Publishing Association

11-13
May, 2011, Aix-en-Provence, France
Table 1. Etching results of the 1 M HF
Voltage Channel depth Etching rate
(V) (μm) (μm/hr)
0.8 18.94 3.788
1 20 4
1.2 19.31 3.862
1.5 14.06 2.812
(2) Etching results of the 2M HF
Figure 7 and Table 2 illustrate the etching results of the
2M HF. As shown in Table 2, the applied voltage of 1V rather
than the 1.5 V produced the fastest etching. It is presumed that
the 1.5 V potential might reduce the effect of the electric field
concentration, resulting in the increasing of the electric hole on
the pore wall. The increasing etching reactions on the pore wall
produced rugged wall surface. Since the etching reactions did
not rivet on the pore tip, the etching rate is thus reduced (Figure
7D).
Figure 8. SEM images of the 4M HF etching results, (A)0.8V; (B)1V; (C)1.2V;
(D)1.5V
Table 3. Etching results of the 4 M HF
Voltage
(V)
Channel depth
(μm)
Etching rate
(μm/hr)
0.8 94.62 18.924
1 56.9 11.38
1.2 22.765 4.553
1.5 36.216 7.2432
Figure 7. SEM images of the 2M HF etching results, (A)0.8V; (B)1V; (C)1.2V;
(D)1.5V
Table 2. Etching results of the 2 M HF
Voltage
(V)
Channel depth
(μm)
Etching rate
(μm/hr)
0.8 29.6 5.92
1 58.984 11.7968
1.2 50.52 10.104
1.5 49.743 9.9486
(3) Etching results of the 4M HF
The 4M HF etching results are shown in Figure 8 and
Table 3. Figure 8 indicates that only the applied voltage of 0.8
V can conduct acceptable etching. Since the concentration of
HF is 4M, a larger applied voltage will draw forth far enough
electric holes on the wafer surface to react with the fluoric ions.
The etching process thus starts randomly from the wafer
surface rather than form the tip of the inverted pyramids (Figure
8B-8D).
3.2 Effect of the protective Si 3 N 4 layer
Electric field concentration is the basic principle of anodic
etching. In the study, the spots of electric field concentration
consist of the tips of the inverted pyramids and the four corners
of etch pre-etched pore. The protective Si 3 N 4 layer further
enhances this phenomenon. It is also interesting to investigate
the influence of the protective Si 3 N 4 layer. The parameters for
Figure 7(B) (HF=2M, applied voltage=1V) which had better
etching performance are used for the etching without a Si 3 N 4
layer.
Figure 9 compares the results of the with Si 3 N 4 layer and the
without Si 3 N 4 layer etchings. The top row and the bottom row
illustrate the results of the without Si 3 N 4 layer and with Si 3 N 4
layer etching, respectively. The etching time of the without
Si 3 N 4 layer etching is 3 hr. The etching rate, which is estimated
to be 11.61 m/hr, is close to that of the with Si 3 N 4 layer etching.
For the without Si 3 N 4 layer etching, randomly etched cavities
due to the reactions between fluoric acids and electron holes on
the silicon surface can be observed. It can also be found that the
wet etched squares are widened. For the Si 3 N 4 layer protective
etching, symmetrical cannelures stretching from the four
corners of etch wet etched square. It is presumed that the
electric field concentration at the corners of a wet etched square
at the initial stage of etching leads to the directional etchings of
the cannelures. However, vertical microchannels having the
size close to the wet etched square were fabricated. It reveals
that a Si 3 N 4 layer is desired for a successful etching of porous
array in silicon.
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