80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
A normally not-ready system is one in which READY remains low at all times except to signal a
ready condition. For any bus cycle, only the selected device drives the READY input high to
complete the bus cycle. The circuit shown in Figure 3-15 illustrates a simple circuit to generate a
normally not-ready signal. Note that if no device is selected the bus remains not-ready indefinitely.
Systems with many slow devices that cannot operate at the maximum bus bandwidth usually
implement a normally not-ready signal.
The start of a bus cycle clears the wait state module and forces READY low. After every rising
edge of CLKOUT, INPUT1 and INPUT2 are shifted through the module and eventually drive
READY high. Assuming INPUT1 and INPUT2 are valid prior to phase 2 of T2, no delay through
the module causes one wait state. Each additional clock delay through the module generates one
additional wait state. Two inputs are used to establish different wait state conditions.
CS1
CS2
CS3
CS4
Wait State Module
Input 1
Input 2
Out
READY
ALE
CLKOUT
Clear
Clock
A1080-0A
Figure 3-15. Generating a Normally Not-Ready Bus Signal
A normally ready signal remains high at all times except when the selected device needs to signal
a not-ready condition. For any bus cycle, only the selected device drives the READY input low
to delay the completion of the bus cycle. The circuit shown in Figure 3-16 illustrates a simple circuit
to generate a normally ready signal. Note that if no device is selected the bus remains
ready. Systems that have few or no devices requiring wait states usually implement a normally
ready signal.
The start of a bus cycle preloads a zero shifter and forces READY active (high). READY remains
active if neither CS1 or CS2 goes low. Should either CS1 or CS2 go low, zeros are shifted out on
every rising edge of CLKOUT, causing READY to go inactive. At the end of the shift pattern,
READY is forced active again. Assuming CS1 and CS2 are active just prior to phase 2 of T2,
shifting one zero through the module causes two wait states. Each additional zero shifted through
the module generates one wait state.
3-16