80C186EC/80C188EC Microprocessor User's Manual

SERIAL COMMUNICATIONS UNIT
The serial port receives BREAK characters of two different lengths. If a BREAK character longer
than M bit-times is detected, the DBRK0 bit in SxSTS is set. If the BREAK character is longer
than 2M+3 bit-times, DBRK1 in SxSTS is set. M is equal to the total number of bits in a frame.
For example, M is equal to 11 (decimal) in Mode 3.
Register Name:
Register Mnemonic:
Register Function:
Serial Status Register
SxSTS
Indicates the status of the serial port.
15 0
D
B
R
K
1
D
B
R
K
0
R
B
8/
P
E
R
I
T
I
F
E
T
X
E
O
E
C
T
S
A1278-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
DBRK1 Detect Break 1 0 Set when a break longer than 2M+3 bits occurs.
DBRK0 Detect Break 0 0 Set when a break longer than M bits occurs.
RB8/PE
RI
TI
Received
Bit8/Parity
Error
Receive
Interrupt
Transmit
Interrupt
0 Contains the 9th received data bit in modes 2
and 3. PE is set when a parity error occurs. PE
is valid only when parity is enabled in Mode 1,
2 or 3.
0 RI is set when a character has been received
and placed in SxRBUF. Note that RI need not
be explicitly cleared to receive more characters.
Writing a one to this bit will not cause an
interrupt.
0 TI is set when a character has finished transmitting.
TI determines when one more
character can be transmitted. Writing a one to
this bit will not cause an interrupt.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 11-14. Serial Port Status Register (SxSTS)
11-16