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80C186EC/80C188EC Microprocessor User's Manual

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SERIAL COMMUNICATIONS UNIT<br />

Register Name:<br />

Register Mnemonic:<br />

Register Function:<br />

Serial Port Control Register<br />

SxCON<br />

Controls serial port operating modes.<br />

15 0<br />

S<br />

B<br />

R<br />

K<br />

T<br />

B<br />

8<br />

C<br />

E<br />

N<br />

R<br />

E<br />

N<br />

E<br />

V<br />

N<br />

P<br />

E<br />

N<br />

M<br />

2<br />

M<br />

1<br />

M<br />

0<br />

A1277-0A<br />

Bit<br />

Mnemonic<br />

Bit Name<br />

Reset<br />

State<br />

Function<br />

SBRK Send Break 0 Setting SBRK drives TXD low. TXD remains low<br />

until SBRK is cleared.<br />

TB8<br />

CEN<br />

REN<br />

EVN<br />

PEN<br />

Transmitted<br />

Bit 8<br />

Clear-to-<br />

Send Enable<br />

Receive<br />

Enable<br />

Even Parity<br />

Select<br />

Parity<br />

Enable<br />

0 TB8 is the eighth data bit transmitted in modes 2<br />

and 3.<br />

0 When CEN is set, no transmissions will occur until<br />

the CTS pin is asserted.<br />

0 Set to enable the receive machine.<br />

0 When parity is enabled, EVN selects between even<br />

and odd parity. Set for even, clear for odd parity.<br />

0 Setting PEN enables the parity generation/checking<br />

for all transmissions/receptions.<br />

M2:0 Serial Port<br />

Mode Field<br />

0 Operating mode for the serial port channel.<br />

M2 M1 M0 Mode<br />

0 0 0 Synchronous Mode0<br />

0 0 1 10-Bit Asynch Mode1<br />

0 1 0 11-Bit Asynch Mode2<br />

0 1 1 11-Bit Asynch Mode3<br />

1 0 0 9-Bit Asynch Mode4<br />

1 0 1 Reserved<br />

1 1 0 Reserved<br />

1 1 1 Reserved<br />

NOTE:<br />

Reserved register bits are shown with gray shading. Reserved bits must be written to<br />

a logic zero to ensure compatibility with future Intel products.<br />

Figure 11-13. Serial Port Control Register (SxCON)<br />

11-15

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