80C186EC/80C188EC Microprocessor User's Manual

OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.3 INTERRUPTS AND EXCEPTION HANDLING
Interrupts and exceptions alter program execution in response to an external event or an error
condition. An interrupt handles asynchronous external events, for example an NMI. Exceptions
result directly from the execution of an instruction, usually an instruction fault. The user can
cause a software interrupt by executing an “INTn” instruction. The CPU processes software interrupts
in the same way that it handles exceptions.
The 80C186 Modular Core responds to interrupts and exceptions in the same way for all devices
within the 80C186 Modular Core family. However, devices within the family may have different
Interrupt Control Units. The Interrupt Control Unit handles all external interrupt sources and presents
them to the 80C186 Modular Core via one maskable interrupt request (see Figure 2-24).
This discussion covers only those areas of interrupts and exceptions that are common to the
80C186 Modular Core family. The Interrupt Control Unit is proliferation-dependent; see Chapter
7, “Interrupt Control Unit,” for additional information.
NMI
Maskable
Interrupt
Request
CPU
Interrupt
Acknowledge
Interrupt
Control
Unit
External
Interrupt
Sources
A1028-0A
Figure 2-24. Interrupt Control Unit
2.3.1 Interrupt/Exception Processing
The 80C186 Modular Core can service up to 256 different interrupts and exceptions. A 256-entry
Interrupt Vector Table (Figure 2-25) contains the pointers to interrupt service routines. Each entry
consists of four bytes, which contain the Code Segment (CS) and Instruction Pointer (IP) of
the first instruction in the interrupt service routine. Each interrupt or exception is given a type
number, 0 through 255, corresponding to its position in the Interrupt Vector Table. Note that interrupt
types 0–31 are reserved for Intel and should not be used by an application program.
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