80C186EC/80C188EC Microprocessor User's Manual

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BUS INTERFACE UNIT 3.3.1 16-Bit Bus Memory and I/O Requirements A 16-bit bus has certain assumptions that must be met to operate properly. Memory used to store instruction operands (i.e., the program) and immediate data must be 16 bits wide. Instruction prefetch bus cycles require that both banks be used. The lower bank contains the even bytes of code and the upper bank contains the odd bytes of code. Memory used to store interrupt vectors and stack data must be 16 bits wide. Memory address space between 0H and 3FFH (1 Kbyte) holds the starting location of an interrupt routine. In response to an interrupt, the BIU fetches two consecutive, even-addressed words from this 1 Kbyte address space. Stack pushes and pops always write or read even-addressed word data. 3.3.2 8-Bit Bus Memory and I/O Requirements An 8-bit bus interface has no restrictions on implementing the memory or I/O interfaces. All transfers, bytes and words, occur over the single 8-bit bus. Operations requiring word transfers automatically execute two consecutive byte transfers. 3.4 BUS CYCLE OPERATION The BIU executes a bus cycle to transfer data between any of the integrated units and any external memory or I/O devices (see Figure 3-6). A bus cycle consists of a minimum of four CPU clocks known as “T-states.” A T-state is bounded by one falling edge of CLKOUT to the next falling edge of CLKOUT (see Figure 3-7). Phase 1 represents the low time of the T-state and starts at the high-to-low transition of CLKOUT. Phase 2 represents the high time of the T-state and starts at the low-to-high transition of CLKOUT. Address, data and control signals generated by the BIU go active and inactive at different phases within a T-state. 3-7
BUS INTERFACE UNIT CLKOUT T4 T1 T2 T3 T4 ALE S2:0 Valid Status AD15:0 Address Data RD / WR A1507-0A Figure 3-6. Typical Bus Cycle CLKOUT TN Falling Edge Rising Edge Phase 1 Phase 2 (Low Phase) (High Phase) A1111-0A Figure 3-7. T-State Relation to CLKOUT Figure 3-8 shows the BIU state diagram. Typically a bus cycle consists of four consecutive T- states labeled T1, T2, T3 and T4. A TI (idle) state occurs when no bus cycle is pending. Multiple T3 states occur to generate wait states. The TW symbol represents a wait state. The operation of a bus cycle can be separated into two phases: • Address/Status Phase • Data Phase 3-8
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Page 41 and 42: OVERVIEW OF THE 80C186 FAMILY ARCHI
Page 84: Bus Interface Unit 3
Page 87 and 88: BUS INTERFACE UNIT Physical Impleme
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Page 91: BUS INTERFACE UNIT For word transfe
Page 95 and 96: BUS INTERFACE UNIT CLKOUT T4 or TI
Page 97 and 98: BUS INTERFACE UNIT Signals From CPU
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Page 107 and 108: BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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Page 115 and 116: BUS INTERFACE UNIT After several TI
Page 117 and 118: BUS INTERFACE UNIT 3.5.5 Temporaril
Page 119 and 120: BUS INTERFACE UNIT CLKOUT ALE T4 T1
Page 121 and 122: BUS INTERFACE UNIT CLKOUT NMI/NTx N
Page 123 and 124: BUS INTERFACE UNIT ALE Processor A1
Page 125 and 126: BUS INTERFACE UNIT The WAIT instruc
Page 127 and 128: BUS INTERFACE UNIT CLKOUT HOLD 1 2
Page 129 and 130: BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
Page 131 and 132: BUS INTERFACE UNIT CLKOUT HOLD 1 2
Page 134: Peripheral Control Block 4
Page 137 and 138: PERIPHERAL CONTROL BLOCK Register N
Page 139 and 140: PERIPHERAL CONTROL BLOCK 4.3 RESERV
Page 141 and 142: PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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