80C186EC/80C188EC Microprocessor User's Manual

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INTERRUPT CONTROL UNIT ;The following section of code shows the polling process ;for the 8259A modules... ; ;For brevity, the Register EQUates are not shown. ; POLL_EXAMPLE SEGMENT ASSUME CS:POLL_EXAMPLE MOV DX, SPICP0 ;POLL Command issued thru OCW3 MOV AX, 0CH ;POLL=1 and D5:4=01 OUT DX, AL ;Issue POLL Command ;The slave 8259A will deposit the poll status byte on the ;next RD# pulse... IN DX, AL ;Read the slave 8259A TEST AL, 80H ;Has there been an interrupt JNE INTERPT ;If D7=1 --> yes! ;If the code gets to here then there has been no interrupt. JMP NO_INTERRUPTS INTERPT: AND AL, 111B ;Get just the interrupt type. ;At this point the interrupt type is in AL. Your code ;would branch to the appropriate routines... POLL_EXMPL ENDS Example 8-3. Using the Poll Command 8-51
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
Page 210 and 211: CHAPTER 8 INTERRUPT CONTROL UNIT Th
Page 212 and 213: INTERRUPT CONTROL UNIT Polling requ
Page 214 and 215: INTERRUPT CONTROL UNIT INT INTA D7:
Page 216 and 217: INTERRUPT CONTROL UNIT Edge Sense L
Page 218 and 219: INTERRUPT CONTROL UNIT 8.3.2 Interr
Page 220 and 221: INTERRUPT CONTROL UNIT 8.3.3.1 Defa
Page 222 and 223: INTERRUPT CONTROL UNIT More than on
Page 224 and 225: INTERRUPT CONTROL UNIT IR0 IR1 IR2
Page 226 and 227: INTERRUPT CONTROL UNIT 10. On the s
Page 228 and 229: INTERRUPT CONTROL UNIT 8.3.7 Altern
Page 230 and 231: INTERRUPT CONTROL UNIT 8.4.2 Progra
Page 232 and 233: INTERRUPT CONTROL UNIT Begin Initia
Page 234 and 235: INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
Page 236 and 237: INTERRUPT CONTROL UNIT Register Nam
Page 242 and 243: INTERRUPT CONTROL UNIT Table 8-2. O
Page 244 and 245: INTERRUPT CONTROL UNIT The ESMM (En
Page 246 and 247: INTERRUPT CONTROL UNIT Internal Int
Page 248 and 249: INTERRUPT CONTROL UNIT To Slave 825
Page 252 and 253: INTERRUPT CONTROL UNIT 8.6.1 Interr
Page 254 and 255: INTERRUPT CONTROL UNIT CPU WR RD GC
Page 256 and 257: INTERRUPT CONTROL UNIT Non-Alike Ac
Page 258 and 259: INTERRUPT CONTROL UNIT ;Now start t
Page 262: Timer/Counter Unit 9
Page 265 and 266: TIMER/COUNTER UNIT T0 In T1 In Tran
Page 267 and 268: TIMER/COUNTER UNIT Start Timer Enab
Page 269 and 270: TIMER/COUNTER UNIT When configured
Page 271 and 272: TIMER/COUNTER UNIT Register Name: R
Page 273 and 274: TIMER/COUNTER UNIT Register Name: R
Page 275 and 276: TIMER/COUNTER UNIT 9.2.2 Clock Sour
Page 277 and 278: TIMER/COUNTER UNIT Table 9-2. Timer
Page 279 and 280: TIMER/COUNTER UNIT The input pins f
Page 281 and 282: TIMER/COUNTER UNIT $mod186 name exa
Page 283 and 284: TIMER/COUNTER UNIT sti ;enable inte
Page 285 and 286: TIMER/COUNTER UNIT pop dx ;restore
Page 288: Direct Memory Access Unit 10
Page 291 and 292: DIRECT MEMORY ACCESS UNIT When the
Page 293 and 294: DIRECT MEMORY ACCESS UNIT 10.1.4 Ex
Page 295 and 296: DIRECT MEMORY ACCESS UNIT Fetch Cyc
Page 297 and 298: DIRECT MEMORY ACCESS UNIT 10.1.7.1
Page 299 and 300: DIRECT MEMORY ACCESS UNIT Timer 2 M
Page 301 and 302: DIRECT MEMORY ACCESS UNIT Timer 2 D
Page 303 and 304: DIRECT MEMORY ACCESS UNIT BIU Reque
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT 10.2.1.8
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DIRECT MEMORY ACCESS UNIT Because o
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DIRECT MEMORY ACCESS UNIT MOV DX, D
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DIRECT MEMORY ACCESS UNIT $mod186 n
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT ; NOW WE
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CHAPTER 11 SERIAL COMMUNICATIONS UN
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SERIAL COMMUNICATIONS UNIT Receptio
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SERIAL COMMUNICATIONS UNIT SxTBUF F
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SERIAL COMMUNICATIONS UNIT TXD/ RXD
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SERIAL COMMUNICATIONS UNIT 11.2 PRO
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Due to i
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SERIAL COMMUNICATIONS UNIT The CPU
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SERIAL COMMUNICATIONS UNIT 11.3.3.2
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SERIAL COMMUNICATIONS UNIT 11.5.2 M
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SERIAL COMMUNICATIONS UNIT MASTER 1
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT cmp al,
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Watchdog Timer Unit 12
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WATCHDOG TIMER UNIT Figure 12-2 sho
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WATCHDOG TIMER UNIT 12.2.2 Watchdog
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WATCHDOG TIMER UNIT 12.3 USING THE
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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Input/Output Ports 13
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS 13.1.4.1 Port 1
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS 13.3 PROGRAMMING
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CHAPTER 14 MATH COPROCESSING The 80
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MATH COPROCESSING 14.3.1.1 Data Tra
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MATH COPROCESSING 14.3.1.3 Comparis
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MATH COPROCESSING 14.3.2 80C187 Dat
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING Bus cycles involv
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MATH COPROCESSING 14.4.4 Exception
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MATH COPROCESSING $mod186 name exam
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ONCE Mode 15
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80C186 Instruction Set Additions an
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX B INPUT SYNCHRONIZATION Ma
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Instruction Set Descriptions C
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS INC IN
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INSTRUCTION SET DESCRIPTIONS OR OUT
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Instruction Set Opcodes and Clock C
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INSTRUCTION SET OPCODES AND CLOCK C
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INDEX 80C187 Math Coprocessor, 14-2
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INDEX registers, 6-5-6-15 system di
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INDEX port 2, 13-6 port 3, 13-7 pro
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INDEX P Packed BCD, defined, 2-37 P
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INDEX SCU asynchronous mode, 11-21-
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80C186EC/80C188EC Microprocessor User's Manual

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