80C186EC/80C188EC Microprocessor User's Manual

CHIP-SELECT UNIT
Table 6-3 lists example wait state and bus ready requirements for overlapping chip-selects and
the resulting requirements for accesses to the overlapped region.
Table 6-3. Example Adjustments for Overlapping Chip-Selects
Chip-Select X Chip-Select Y Overlapped Region Access
Wait States Bus Ready Wait States Bus Ready Wait States Bus Ready
3 ignored 9 ignored 9 ignored
5 required 0 ignored 0 required
2 required 2 required 2 required
Be cautious when overlapping chip-selects with different wait state or bus ready programming.
The following two conditions require special attention to ensure proper system operation:
1. When all overlapping chip-selects ignore bus ready but have different wait states, verify
that each chip-select still works properly using the highest wait state value. A system
failure may result when too few or too many wait states occur in the bus cycle.
2. If one or more of the overlapping chip-selects requires bus ready, verify that all chipselects
that ignore bus ready still work properly using both the smallest wait state value
and the longest possible bus cycle. A system failure may result when too few or too many
wait states occur in the bus cycle.
6.4.7 Memory or I/O Bus Cycle Decoding
The Chip-Select Unit decodes bus cycle status and address information to determine whether a
chip-select goes active. The MEM control bit in the STOP register defines whether memory or
I/O address space is decoded. Memory address space accesses consist of memory read, memory
write and instruction prefetch bus cycles. I/O address space accesses consist of I/O read and I/O
write bus cycles.
Chip-selects go active for bus cycles initiated by the CPU, DMA Control Unit and Refresh Control
Unit.
6.4.8 Programming Considerations
When programming chip-selects active for I/O bus cycles, remember that eight bytes of I/O are
reserved by Intel. These eight bytes (locations 00F8H through 00FFH) control the interface to an
80C187 math coprocessor. A chip-select can overlap this reserved space provided there is no intention
of using the 80C187. However, to avoid possible future compatibility issues, Intel recommends
that no chip-select start at I/O address location 00C0H.
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