80C186EC/80C188EC Microprocessor User's Manual

INSTRUCTION SET DESCRIPTIONS
Table C-4. Instruction Set (Continued)
Name Description Operation
Flags
Affected
WAIT Wait:
WAIT
Causes the CPU to enter the wait state
while its test line is not active.
Instruction Operands:
none
XCHG
NOTE:
Exchange:
XCHG dest, src
Switches the contents of the source
and destination operands (bytes or
words). When used in conjunction with
the LOCK prefix, XCHG can test and
set a semaphore that controls access
to a resource shared by multiple
processors.
Instruction Operands:
XCHG accum, reg
XCHG mem, reg
XCHG reg, reg
None AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
(temp) ← (dest)
(dest) ← (src)
(src) ← (temp)
The three symbols used in the Flags Affected column are defined as follows:
– the contents of the flag remain unchanged after the instruction is executed
the contents of the flag is undefined after the instruction is executed
üthe flag is updated after the instruction is executed
AF –
CF –
DF –
IF –
OF –
PF –
SF –
TF –
ZF –
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