80C186EC/80C188EC Microprocessor User's Manual

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WATCHDOG TIMER UNIT A LOCKed instruction sequence that is similar to the reload sequence disables the Watchdog Timer. The Watchdog Timer Disable (WDTDIS) Register expects a sequence of two bytes, which must be written by a single LOCKed instruction. The first byte must be 55H and the second must be 0AAH (the reverse of the reload sequence). Writing any other data values or using two separate LOCKed instructions will not disable the WDT. The Watchdog Timer cannot be disabled once it has been reloaded by the system software. Similarly, it cannot be enabled once it has been disabled. Examples 12-3 and 12-4 show the code necessary to disable the Watchdog Timer Unit when the Peripheral Control Block is located in I/O and memory space, respectively. wdt_data segment wdt_off DB 055H, 0AAH wdt_data wdt_code ends segment assume cs:wdt_code mov ax, seg wdt_off mov es, ax mov si, offset wdt_off mov dx, WDTDIS ;ES:SI points to wdt_key ;disable value of WDT cld ;clear direction flag (autoincrement) mov cx, 2 ;2 bytes will be written lock rep outsb es:[si], dx ;LOCKed disable sequence. ;The WDT is disabled wdt_code ends Example 12-3. Disabling the Watchdog Timer (Peripheral Control Block in I/O Space) 12-7
WATCHDOG TIMER UNIT wdt_data segment wdt_off DB 055H, 0AAH wdt_data pcb_image ends segment;image of PCB WDTDIS EQU XXXXH ;replace “XXXX” with appropriate ;offset from PCB+0. WDTDIS DW pcb_image wdt_code ends segment assume cs:wdt_code mov mov mov ax, seg wdt_off ds, ax si, offset wdt_off ;DS:SI = address of disable ;value for the WDT mov ax, seg WDTDIS mov es, ax mov di, offset WDTDIS ;ES:DI = address of WDTDIS register cld ;clear direction flag(autoincrement) mov cx, 2 ;2 bytes in sequence lock rep movsb ;LOCKed disable sequence ;The WDT down counter ;has been disabled. wdt_code ends Example 12-4. Disabling the Watchdog Timer (Peripheral Control Block in Memory Space) 12.5 WATCHDOG TIMER REGISTERS Six Peripheral Control Block Registers control the Watchdog Timer Unit. The Watchdog Timer Reload Value is held in two 16-bit registers: WDTRLDH (Figure 12-5) and WDTRLDL (Figure 12-6). The value in the 32-bit down counter can be read from the count registers, WDTCNTH (Figure 12-7) and WDTCNTL (Figure 12-8). The count registers are read only. The WDT Clear (WDTCLR) and WDT Disable (WDTDIS) registers are not shown, as their functions are described in the text and are not tied to specific bit positions. “Reloading the Watchdog Timer Down Counter” on page 12-3 describes the WDT Clear register, and “Disabling the Watchdog Timer” on page 12-6 discusses the WDT Disable register. 12-8
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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Page 328: Serial Communications Unit 11
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Page 364 and 365: CHAPTER 12 WATCHDOG TIMER UNIT Syst
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Page 380 and 381: CHAPTER 13 INPUT/OUTPUT PORTS Many
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Page 388 and 389: INPUT/OUTPUT PORTS Register Name: R
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Page 392: Math Coprocessing 14
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Page 412: CHAPTER 15 ONCE MODE ONCE (pronounc
Page 416 and 417: APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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