80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
Register Name: Operation Command Word 2
Register Mnemonic: OCW2 (accessed through MPICP0, SPICP0)
Register Function: Priority and EOI commands
15 0
R
S
L
E
O
I
0
0
L
2
L
1
L
0
A1225-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
R Rotate X This bit combines with the SL and EOI bits to
create a 3-bit instruction field. See Table 8-2.
SL
Specific
Level
X
This bit combines with the R and EOI bits to
create a 3-bit instruction field. See Table 8-2.
EOI
End-of-
Interrupt
X
This bit combines with the R and SL bits to
create a 3-bit instruction field. See Table 8-2.
L2:0 IR Level XXX These bits specify the interrupt level that the
instruction (see Table 8-2) is to act upon. When
the bits are not used by an OCW2 instruction,
they are “don’t care” values.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 8-18. OCW2 Register
Table 8-2. OCW2 Instruction Field Decoding
R SL EOI Command
0 0 0 Rotate in Automatic EOI Mode (Clear)
0 0 1 Non-Specific EOI Command
0 1 0 No Operation
0 1 1 Specific EOI *
1 0 0 Rotate in Automatic EOI Mode (Set)
* These commands use the L2:0 field
8-32