80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
A typical sequence takes place as follows:
1. A low-to-high transition on IR4 sets bit 4 in the Interrupt Request Register.
2. The Priority Resolver checks whether any bits are set in the Interrupt Request Register
that are of a higher priority than IR4. There are none.
3. Because the 8259A module is in Fully Nested Mode, the Priority Resolver checks whether
any bits are set in the In-Service Register that have priority greater than or equal to IR4.
There are none. This step prevents the interruption of higher-priority interrupt handlers by
lower-priority sources.
4. At this point, the Priority Resolver has determined that IR4 has sufficient priority to
interrupt the CPU. The interrupt request line to the CPU is asserted to signal an external
interrupt request.
5. The CPU signals acknowledgment of the interrupt by initiating an interrupt acknowledge
cycle.
6. On the first falling edge of INTA, the 8259A module sets the In-Service Bit for IR4.
Simultaneously, the Interrupt Request Bit is reset. The 8259A module is not driving the
data bus during this phase of the cycle.
7. On the second falling edge of INTA, the 8259A module drives the interrupt type corresponding
to IR4 on the data bus. The 8259A module floats its data bus when INTA goes
high. The interrupt request signal to the CPU is deasserted.
8. The CPU executes the interrupt processing sequence and begins to execute the interrupt
handler for IR4.
9. During execution of the IR4 handler, IR6 goes high, setting bit 6 in the Interrupt Request
Register.
10. The Priority Resolver sees that IR6 is of lower priority than IR4, which is currently being
serviced (IR4’s In-Service bit is set). Because IR6 is of lower priority than IR4, no
interrupt request is sent to the CPU. If IR6 were set to a higher priority than IR4, the IR4
handler would be interrupted.
11. The IR4 handler completes execution. The final instructions of the handler issue an Endof-Interrupt
(EOI) command to the 8259A module. The EOI command clears the In-
Service bit IR4. This completes the servicing of IR4.
12. The Priority Resolver now sees that IR6 is still pending and that no other higher-priority
interrupts are pending or in-service. The 8259A module raises the interrupt request line
again, starting another INTA cycle.
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