80C186EC/80C188EC Microprocessor User's Manual

CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
Chip-Select Start Register
UCSST, LCSST, GCSxST (x=0-7)
Defines chip-select start address and number of
bus wait states.
15 0
C
S
9
C
S
8
C
S
7
C
S
6
C
S
5
C
S
4
C
S
3
C
S
2
C
S
1
C
S
0
W
S
3
W
S
2
W
S
1
W
S
0
A1163-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
CS9:0
Start
Address
3FFH
Defines the starting (base) address for the chipselect.
CS9:0 are compared with the A19:10
(memory bus cycles) or A15:6 (I/O bus cycles)
address bits. An equal to or greater than result
enables the chip-select.
WS3:0
Wait State
Value
0FH
WS3:0 define the minimum number of wait
states inserted into the bus cycle. A zero value
means no wait states. Additional wait states
can be inserted into the bus cycle using bus
ready.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 6-5. START Register Definition
6-7