80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
Because of its 8-bit data bus, the 80C188 Modular Core can transfer only one byte per DMA cycle.
Therefore, the maximum transfer rates for the 80C188 Modular Core are half those calculated
by the equations for the 80C186 Modular Core.
10.3.4 Generating a DMA Acknowledge
The DMA channels do not provide a distinct DMA acknowledge signal. A chip-select line can be
programmed to activate for the memory or I/O range that requires the acknowledge. The chipselect
must be programmed to activate only when a DMA is in progress. Latched status line S6
can be used as a qualifier to the chip-select for situations in which the chip-select line will be active
for both DMA and normal data accesses.
10.4 DMA UNIT EXAMPLES
Example 10-1 sets up channel 0 to perform an unsynchronized burst transfer from memory to
memory while channel 1 is used to service an external DMA request from a hard disk controller.
Example 10-2 shows the steps necessary to use the DMA Unit with the Serial Communications
Unit. Two DMA channels are used: one for transmit and one for receive functions.
Example 10-3 shows timed DMA transfers. A sawtooth waveform is created using DMA transfers
to an A/D converter.
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