80C186EC/80C188EC Microprocessor User's Manual

INTERRUPT CONTROL UNIT
Polling requires that the CPU check each peripheral device in the system periodically to see
whether it requires servicing. It would not be unusual to poll a low-speed peripheral (a serial port,
for instance) thousands of times before it required servicing. In most cases, the use of polling has
a detrimental effect on system throughput. Any time used to check the peripherals is time spent
away from the main processing tasks.
Interrupts eliminate the need for polling by signalling the CPU that a peripheral device requires
servicing. The CPU then stops executing the main task, saves its state and transfers execution to
the peripheral-servicing code (the interrupt handler). At the end of the interrupt handler, the
CPU’s original state is restored and execution continues at the point of interruption in the main
task.
The 80C186 Modular Core has a single maskable interrupt input. (See “Interrupts and Exception
Handling” on page 2-39.) Expanding the interrupt capabilities of the CPU beyond that of a single
source requires an interrupt controller. The controller acts like a filter between the multiple interrupt
request inputs and the single interrupt request to the CPU. The interrupt controller decides
which of the interrupt requests is the most important (has the highest priority) and presents that
interrupt to the CPU. Upon receipt of an interrupt, the CPU begins execution of a handshaking
sequence called the interrupt acknowledge cycle.
The interrupt acknowledge (or INTA) cycle) consists of two locked back-to-back bus cycles that
the CPU initiates upon receipt of an unmasked external interrupt. The INTA cycle (Figure 8-2)
is a specialized read cycle during which the CPU fetches the interrupt vector type from the interrupt
controller. Interrupt acknowledge cycle timings and waveforms are covered in detail in
Chapter 3, “Bus Interface Unit.”
INTA
Data Bus
Vector Type
Valid
A1228-0A
Figure 8-2. Interrupt Acknowledge Cycle
Once the CPU has the vector type, it executes the interrupt processing sequence:
1. Saves a partial machine status by pushing the Processor Status Word onto the stack.
2. Clears the Trap Flag bit and Interrupt Enable bit in the Processor Status Word. This
prevents maskable interrupts or single-step exceptions from interrupting the processor
during the interrupt service routine.
3. Pushes the current CS and IP onto the stack.
8-3