80C186EC/80C188EC Microprocessor User's Manual

DIRECT MEMORY ACCESS UNIT
Both Requests Asserted
Channel
Priority
Synch
0
Low
SRC
1
Low
SRC
Channel 1 Channel 0 Channel 1 Channel 0
Etc.
Channel
Priority
Synch
Channel
Priority
Synch
0
High
SRC
0
High
Dest
1
Low
SRC
1
Low
SRC
Channel 0
Channel 0
Channel 0 Channel 1 Channel 1
Channel 0 Completes
All Transfers
Channel 1 Channel 0 Channel 1
Destination Synch Releases Bus
Etc.
Etc.
A1190-0A
Figure 10-6. Examples of DMA Priority
10.1.10.1.2 Rotating Priority
Channel priority rotates when the channels are programmed as both high or both low priority. The
highest priority is initially assigned to channel 1 of the module. After a channel performs a transfer,
it is assigned the lower priority. When requests are active for both channels, the transfers alternate
between the two.
10.1.10.1.3 The Internal DMA Request Multiplexer
The source of internal DMA requests for a module is selected by the Internal DMA Request Multiplexer.
The multiplexer controls the routing of internal DMA requests to each channel of the
module. When the multiplexer is programmed to select Timer 2 DMA requests, the internal request
line of each channel is connected to Timer 2. When the multiplexer is programmed to select
serial port DMA requests, channel 0 is connected to the transmitter DMA request and channel 1
is connected to the receiver DMA request. A simplified diagram of the Internal DMA Request
Multiplexer is shown in Figure 10-7.
It is important to note that the Internal DMA Request Multiplexer only selects the source of internal
DMA requests; it does not control whether the channel responds to internal or external
DMA requests.
10-11