80C186EC/80C188EC Microprocessor User's Manual

BUS INTERFACE UNIT
Figure 3-20 illustrates a typical 16-bit interface connection to a read-only device interface. The
same example applies to an 8-bit bus system, except that no devices connect to an upper bus. Four
parameters (Table 3-3) must be evaluated when determining the compatibility of a memory (or
I/O) device. T ADLTCH defines the delay through the address latch.
Table 3-3. Read Cycle Critical Timing Parameters
Memory Device
Parameter
Description
Equation
T OE Output enable (RD low) to data valid 2T – T CLOV2 – T CLIS
T ACC
Address valid to data valid 3T – T CLOV2
–T ADLTCH – T CLIS
T CE
Chip enable (UCS) to data valid 3T – T CLOV2
– T CLIS
T DF Output disable (RD high) to output float T RHAX
T OE , T ACC and T CE define the maximum data access requirements for the memory device. These
device parameters must be less than the value calculated in the equation column. An equal to or
greater than result indicates that wait states must be inserted into the bus cycle.
T DF determines the maximum time the memory device can float its outputs before the next bus
cycle begins. A T DF value greater than the equation result indicates a buffer fight. A buffer fight
means two (or more) devices are driving the bus at the same time. This can lead to short circuit
conditions, resulting in large current spikes and possible device damage.
T RHAX cannot be lengthened (other than by slowing the clock rate). To resolve a buffer fight condition,
choose a faster device or buffer the AD bus (see “Buffering the Data Bus” on page 3-37).
3-21