80C186EC/80C188EC Microprocessor User's Manual

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INTERRUPT CONTROL UNIT INT INTA D7:0 RD WR A0 CS Data Bus Buffer and Read/Write Logic Control Logic Internal Bus CAS2:0 Cascade Buffer/ Comparator In-service Register Priority Resolver Interrupt Request Register IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Interrupt Mask Register A1239-0A Figure 8-3. 8259A Module Block Diagram Pending interrupt requests are posted in the Interrupt Request Register. The Interrupt Request Register contains one bit for each of the eight Interrupt Request (IR) signals. When an interrupt request is asserted, the corresponding Interrupt Request Register bit is set. The 8259A module can be programmed to recognize either an active high level or a positive transition on the interrupt request lines. (See “Edge and Level Triggering” on page 8-9.) 8-5
INTERRUPT CONTROL UNIT The Interrupt Request Register bits feed into the Priority Resolver. The Priority Resolver decides which of the pending interrupt requests is the highest priority based on the programmed operating mode. The Priority Resolver controls the interrupt request line to the CPU. The Priority Resolver has a default priority scheme that places IR0 as the highest priority and IR7 as the lowest priority. The priority can be modified through software. (See “The Priority Resolver and Priority Resolution” on page 8-10.) When an interrupt is acknowledged, an In-Service Register bit is set for that specific interrupt source. In some operating modes, the Priority Resolver looks at the In-Service Register in order to make its decision. In Fully Nested Mode, for example, the Priority Resolver needs to know whether a higher-priority interrupt is already in service before it interrupts the CPU. An interrupt handler must explicitly clear the In-Service bit for its interrupt before returning control to the main task. (See “The In-Service Register” on page 8-12.) The Interrupt Mask Register contains one bit for each interrupt request (IR) line. The Interrupt Mask Register allows the selective disabling of individual interrupt request sources. (See “Masking Interrupts” on page 8-14.) An interrupt request line is also referred to as an interrupt level. For example, an interrupt on IR line 7 is also called a “level 7 interrupt.” Figure 8-4 shows a simplified logic diagram for the circuitry for one IR line (or priority cell). Multiple 8259A modules can be connected together to expand the interrupt processing capability beyond eight levels. (See “Cascading 8259As” on page 8-14.) The Cascade Buffer/Comparator is used only when the 8259A module is programmed for cascade mode. During an INTA cycle, the Cascade Buffer of the master 8259A drives the address of the slave 8259A module that is being acknowledged. Each slave 8259A module uses the Cascade Comparator to determine whether it is the addressed slave. 8.3.1 A Typical Interrupt Sequence Using the 8259A Module The function of the 8259A module is best illustrated by an example. For this example we assume the simplest of 8259A module configurations: a single master with the default fixed priority and programmed for Fully Nested Mode. The initial conditions are as follows: • the 8259A has just been initialized • there are no pending interrupts • all interrupts are unmasked • the IR inputs are programmed as edge-sensitive lines 8-6
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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Page 163 and 164: CLOCK GENERATION AND POWER MANAGEME
Page 172 and 173: CHAPTER 6 CHIP-SELECT UNIT Every sy
Page 174 and 175: CHIP-SELECT UNIT Stop Value Ignore
Page 176 and 177: CHIP-SELECT UNIT Address 1 Ready Fl
Page 178 and 179: CHIP-SELECT UNIT Register Name: Reg
Page 180 and 181: CHIP-SELECT UNIT Register Name: Reg
Page 182 and 183: CHIP-SELECT UNIT In the previous eq
Page 184 and 185: CHIP-SELECT UNIT No Any READY = 1 W
Page 186 and 187: CHIP-SELECT UNIT The GCS chip-selec
Page 188 and 189: CHIP-SELECT UNIT $ TITLE (Chip-Sele
Page 190 and 191: CHIP-SELECT UNIT ;SET UP CHIP SELEC
Page 192: Refresh Control Unit 7
Page 195 and 196: REFRESH CONTROL UNIT 7.1 THE ROLE O
Page 197 and 198: REFRESH CONTROL UNIT The BIU does n
Page 199 and 200: REFRESH CONTROL UNIT CLKOUT T4 T1 T
Page 201 and 202: REFRESH CONTROL UNIT 7.7.2.1 Refres
Page 203 and 204: REFRESH CONTROL UNIT Register Name:
Page 205 and 206: REFRESH CONTROL UNIT $mod186 name e
Page 207 and 208: REFRESH CONTROL UNIT T1 T1 T1 T1 T1
Page 210 and 211: CHAPTER 8 INTERRUPT CONTROL UNIT Th
Page 212 and 213: INTERRUPT CONTROL UNIT Polling requ
Page 216 and 217: INTERRUPT CONTROL UNIT Edge Sense L
Page 218 and 219: INTERRUPT CONTROL UNIT 8.3.2 Interr
Page 220 and 221: INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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Page 224 and 225: INTERRUPT CONTROL UNIT IR0 IR1 IR2
Page 226 and 227: INTERRUPT CONTROL UNIT 10. On the s
Page 228 and 229: INTERRUPT CONTROL UNIT 8.3.7 Altern
Page 230 and 231: INTERRUPT CONTROL UNIT 8.4.2 Progra
Page 232 and 233: INTERRUPT CONTROL UNIT Begin Initia
Page 234 and 235: INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
Page 236 and 237: INTERRUPT CONTROL UNIT Register Nam
Page 242 and 243: INTERRUPT CONTROL UNIT Table 8-2. O
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Page 248 and 249: INTERRUPT CONTROL UNIT To Slave 825
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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