80C186EC/80C188EC Microprocessor User's Manual

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DIRECT MEMORY ACCESS UNIT Both Requests Asserted Channel Priority Synch 0 Low SRC 1 Low SRC Channel 1 Channel 0 Channel 1 Channel 0 Etc. Channel Priority Synch Channel Priority Synch 0 High SRC 0 High Dest 1 Low SRC 1 Low SRC Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 0 Completes All Transfers Channel 1 Channel 0 Channel 1 Destination Synch Releases Bus Etc. Etc. A1190-0A Figure 10-6. Examples of DMA Priority 10.1.10.1.2 Rotating Priority Channel priority rotates when the channels are programmed as both high or both low priority. The highest priority is initially assigned to channel 1 of the module. After a channel performs a transfer, it is assigned the lower priority. When requests are active for both channels, the transfers alternate between the two. 10.1.10.1.3 The Internal DMA Request Multiplexer The source of internal DMA requests for a module is selected by the Internal DMA Request Multiplexer. The multiplexer controls the routing of internal DMA requests to each channel of the module. When the multiplexer is programmed to select Timer 2 DMA requests, the internal request line of each channel is connected to Timer 2. When the multiplexer is programmed to select serial port DMA requests, channel 0 is connected to the transmitter DMA request and channel 1 is connected to the receiver DMA request. A simplified diagram of the Internal DMA Request Multiplexer is shown in Figure 10-7. It is important to note that the Internal DMA Request Multiplexer only selects the source of internal DMA requests; it does not control whether the channel responds to internal or external DMA requests. 10-11
DIRECT MEMORY ACCESS UNIT Timer 2 DMA Request Serial Transmitter DMA Request A B S Q Internal DMA Request For Channel 0 Serial Receiver DMA Request A B S Q Internal DMA Request For Channel 1 Select (From Internal DMA Request Multiplexer Register) A1183-0A Figure 10-7. Internal DMA Request Multiplexer 10.1.11 DMA Module Integration The DMA Unit of the <strong>80C186EC</strong>/C188EC consists of two DMA modules (a total of four channels) and the Inter-Module Arbitration Circuitry (see Figure 10-8). 10-12
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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Page 258 and 259: INTERRUPT CONTROL UNIT ;Now start t
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Page 264 and 265: CHAPTER 9 TIMER/COUNTER UNIT The Ti
Page 266 and 267: TIMER/COUNTER UNIT Timer 0 Timer 1
Page 268 and 269: TIMER/COUNTER UNIT Continued From "
Page 270 and 271: TIMER/COUNTER UNIT Register Name: R
Page 276 and 277: TIMER/COUNTER UNIT The timer counti
Page 278 and 279: TIMER/COUNTER UNIT Timer 0 Serviced
Page 280 and 281: TIMER/COUNTER UNIT 9.3.2 Synchroniz
Page 282 and 283: TIMER/COUNTER UNIT lib_80186 segmen
Page 284 and 285: TIMER/COUNTER UNIT $mod186 name exa
Page 286: TIMER/COUNTER UNIT _CMPB equ word p
Page 290 and 291: CHAPTER 10 DIRECT MEMORY ACCESS UNI
Page 292 and 293: DIRECT MEMORY ACCESS UNIT 10.1.1.1
Page 298 and 299: DIRECT MEMORY ACCESS UNIT The Chip-
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Page 306 and 307: DIRECT MEMORY ACCESS UNIT Register
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Page 314 and 315: DIRECT MEMORY ACCESS UNIT The trans
Page 316 and 317: DIRECT MEMORY ACCESS UNIT 10.2.4 Su
Page 318 and 319: DIRECT MEMORY ACCESS UNIT 10.3.1 DR
Page 320 and 321: DIRECT MEMORY ACCESS UNIT $MOD186 n
Page 322 and 323: DIRECT MEMORY ACCESS UNIT SECTORS M
Page 324 and 325: DIRECT MEMORY ACCESS UNIT XOR AX, A
Page 326 and 327: DIRECT MEMORY ACCESS UNIT $mod186 n
Page 328: Serial Communications Unit 11
Page 331 and 332: SERIAL COMMUNICATIONS UNIT 1 2 3 4
Page 333 and 334: SERIAL COMMUNICATIONS UNIT The RX m
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Page 337 and 338: SERIAL COMMUNICATIONS UNIT 5. At th
Page 339 and 340: SERIAL COMMUNICATIONS UNIT Register
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Page 347 and 348: SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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