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80C186EC/80C188EC Microprocessor User's Manual

80C186EC/80C188EC Microprocessor User's Manual

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OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE<br />

Immediate operands are constant data contained in an instruction. Immediate data can be either<br />

8 or 16 bits in length. Immediate operands are available directly from the instruction queue and<br />

can be accessed quickly. As with a register operand, no bus cycles need to be run to get an immediate<br />

operand. Immediate operands can be only source operands and must have a constant value.<br />

2.2.2.2 Memory Addressing Modes<br />

Although the Execution Unit has direct access to register and immediate operands, memory operands<br />

must be transferred to and from the CPU over the bus. When the Execution Unit needs to<br />

read or write a memory operand, it must pass an offset value to the Bus Interface Unit. The Bus<br />

Interface Unit adds the offset to the shifted contents of a segment register, producing a 20-bit<br />

physical address. One or more bus cycles are then run to access the operand.<br />

The offset that the Execution Unit calculates for memory operand is called the operand’s Effective<br />

Address (EA). This address is an unsigned 16-bit number that expresses the operand’s distance,<br />

in bytes, from the beginning of the segment in which it resides. The Execution Unit can<br />

calculate the effective address in several ways. Information encoded in the second byte of the instruction<br />

tells the Execution Unit how to calculate the effective address of each memory operand.<br />

A compiler or assembler derives this information from the instruction written by the programmer.<br />

Assembly language programmers have access to all addressing modes.<br />

The Execution Unit calculates the Effective Address by summing a displacement, the contents of<br />

a base register and the contents of an index register (see Figure 2-12). Any combination of these<br />

can be present in a given instruction. This allows a variety of memory addressing modes.<br />

2-28

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