80C186EC/80C188EC Microprocessor User's Manual

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INTRODUCTION 1.5 PRODUCT LITERATURE You can order product literature from the following Intel literature centers. 1-800-468-8118, ext. 283 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only) 1.6 TRAINING CLASSES In the U.S. and Canada, you can register for training classes through the Intel customer training center. Classes are held in the U.S. 1-800-234-8806 U.S. and Canada 1-7
Page 1 and 2: 80C186EC/80C188EC Microprocessor Us
Page 3 and 4: Information in this document is pro
Page 5 and 6: CONTENTS 2.3 INTERRUPTS AND EXCEPTI
Page 7 and 8: CONTENTS 6.4 PROGRAMMING...........
Page 9 and 10: CONTENTS CHAPTER 9 TIMER/COUNTER UN
Page 11 and 12: CONTENTS 11.4 SERIAL COMMUNICATIONS
Page 13 and 14: CONTENTS FIGURES Figure Page 2-1 Si
Page 15 and 16: CONTENTS FIGURES Figure Page 6-6 ST
Page 17 and 18: CONTENTS FIGURES Figure Page 11-18
Page 19 and 20: CONTENTS Table TABLES Page C-1 Inst
Page 22: Introduction 1
Page 25 and 26: INTRODUCTION The 80C186 Modular Cor
Page 27 and 28: INTRODUCTION Table 1-2. Related Doc
Page 29: INTRODUCTION 1.3.2.1 How to Find Ap
Page 34 and 35: CHAPTER 2 OVERVIEW OF THE 80C186 FA
Page 36 and 37: OVERVIEW OF THE 80C186 FAMILY ARCHI
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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CHAPTER 3 BUS INTERFACE UNIT The Bu
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BUS INTERFACE UNIT Y + 1 X + 1 Even
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BUS INTERFACE UNIT (X + 1) First Bu
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BUS INTERFACE UNIT 3.3.1 16-Bit Bus
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BUS INTERFACE UNIT The address/stat
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BUS INTERFACE UNIT T4 or TI T1 T2 C
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BUS INTERFACE UNIT 3.4.2 Data Phase
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BUS INTERFACE UNIT T1 T2 T3 TW TW T
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BUS INTERFACE UNIT Wait State Modul
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BUS INTERFACE UNIT T2 T3 TW T4 CLKO
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BUS INTERFACE UNIT Figure 3-20 illu
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BUS INTERFACE UNIT UCS AD7:0 LA15:1
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BUS INTERFACE UNIT Most memory and
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BUS INTERFACE UNIT CLKOUT T1 T2 T3
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BUS INTERFACE UNIT 3.5.4 HALT Bus C
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BUS INTERFACE UNIT CLKOUT T1 TI TI
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BUS INTERFACE UNIT CLKOUT ALE S2:0
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BUS INTERFACE UNIT CLKOUT ALE 8 1/2
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BUS INTERFACE UNIT 3.6.1 Buffering
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BUS INTERFACE UNIT AD15:8 8 A DEN G
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BUS INTERFACE UNIT In general, pref
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BUS INTERFACE UNIT The major factor
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BUS INTERFACE UNIT +5 +5 PRE D Q La
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BUS INTERFACE UNIT 6. Internal erro
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CHAPTER 4 PERIPHERAL CONTROL BLOCK
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PERIPHERAL CONTROL BLOCK Table 4-1.
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PERIPHERAL CONTROL BLOCK 4.4.3 F-Bu
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PERIPHERAL CONTROL BLOCK As an exam
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CHAPTER 5 CLOCK GENERATION AND POWE
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CLOCK GENERATION AND POWER MANAGEME
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Chip-Select Unit 6
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CHIP-SELECT UNIT 27C256 74AC138 A1:
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CHIP-SELECT UNIT T4 T1 T2 T3 T4 CLK
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CHIP-SELECT UNIT The START register
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT 6.4.2 Start Addres
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CHIP-SELECT UNIT BUS READY READY Co
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CHIP-SELECT UNIT Table 6-3 lists ex
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CHIP-SELECT UNIT Processor READY AL
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CHIP-SELECT UNIT DRAM_BASEEQU 128 ;
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CHIP-SELECT UNIT ; DATA SEGMENT DAT
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CHAPTER 7 REFRESH CONTROL UNIT The
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REFRESH CONTROL UNIT Refresh Contro
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REFRESH CONTROL UNIT 7.5 REFRESH BU
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REFRESH CONTROL UNIT 7.7 PROGRAMMIN
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT mov dx, RFBASE
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Interrupt Control Unit 8
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INTERRUPT CONTROL UNIT Master 8259A
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INTERRUPT CONTROL UNIT 4. Fetches t
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INTERRUPT CONTROL UNIT The Interrup
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INTERRUPT CONTROL UNIT A typical se
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INTERRUPT CONTROL UNIT 8.3.2.3 Spur
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INTERRUPT CONTROL UNIT 8.3.3.3 Chan
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INTERRUPT CONTROL UNIT Use of Autom
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INTERRUPT CONTROL UNIT 8.3.6.2 The
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INTERRUPT CONTROL UNIT 8.3.6.6 Spur
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INTERRUPT CONTROL UNIT 8.3.9 Altern
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INTERRUPT CONTROL UNIT Initializati
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT 8.4.3.4 ICW3
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INTERRUPT CONTROL UNIT 8.4.4 The Op
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INTERRUPT CONTROL UNIT 8.4.4.3 Spec
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INTERRUPT CONTROL UNIT 8.5 MODULE I
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INTERRUPT CONTROL UNIT Timer 0 High
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INTERRUPT CONTROL UNIT 8.5.1.4 Usin
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INTERRUPT CONTROL UNIT IR Line T IR
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INTERRUPT CONTROL UNIT The AD15:13
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INTERRUPT CONTROL UNIT ;We begin wi
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INTERRUPT CONTROL UNIT ;The followi
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Timer/Counter Unit 9
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TIMER/COUNTER UNIT T0 In T1 In Tran
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TIMER/COUNTER UNIT Start Timer Enab
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TIMER/COUNTER UNIT When configured
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT 9.2.2 Clock Sour
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TIMER/COUNTER UNIT Table 9-2. Timer
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TIMER/COUNTER UNIT The input pins f
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT sti ;enable inte
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TIMER/COUNTER UNIT pop dx ;restore
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Direct Memory Access Unit 10
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DIRECT MEMORY ACCESS UNIT When the
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DIRECT MEMORY ACCESS UNIT 10.1.4 Ex
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DIRECT MEMORY ACCESS UNIT Fetch Cyc
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DIRECT MEMORY ACCESS UNIT 10.1.7.1
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DIRECT MEMORY ACCESS UNIT Timer 2 M
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DIRECT MEMORY ACCESS UNIT Timer 2 D
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DIRECT MEMORY ACCESS UNIT BIU Reque
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT 10.2.1.8
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DIRECT MEMORY ACCESS UNIT Because o
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DIRECT MEMORY ACCESS UNIT MOV DX, D
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DIRECT MEMORY ACCESS UNIT $mod186 n
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT ; NOW WE
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CHAPTER 11 SERIAL COMMUNICATIONS UN
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SERIAL COMMUNICATIONS UNIT Receptio
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SERIAL COMMUNICATIONS UNIT SxTBUF F
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SERIAL COMMUNICATIONS UNIT TXD/ RXD
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SERIAL COMMUNICATIONS UNIT 11.2 PRO
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Due to i
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SERIAL COMMUNICATIONS UNIT The CPU
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SERIAL COMMUNICATIONS UNIT 11.3.3.2
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SERIAL COMMUNICATIONS UNIT 11.5.2 M
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SERIAL COMMUNICATIONS UNIT MASTER 1
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT cmp al,
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Watchdog Timer Unit 12
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WATCHDOG TIMER UNIT Figure 12-2 sho
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WATCHDOG TIMER UNIT 12.2.2 Watchdog
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WATCHDOG TIMER UNIT 12.3 USING THE
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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Input/Output Ports 13
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS From Integrated
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INPUT/OUTPUT PORTS 13.1.4.1 Port 1
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS 13.3 PROGRAMMING
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CHAPTER 14 MATH COPROCESSING The 80
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MATH COPROCESSING 14.3.1.1 Data Tra
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MATH COPROCESSING 14.3.1.3 Comparis
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MATH COPROCESSING 14.3.2 80C187 Dat
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING Bus cycles involv
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MATH COPROCESSING 14.4.4 Exception
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MATH COPROCESSING $mod186 name exam
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ONCE Mode 15
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80C186 Instruction Set Additions an
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80C186 INSTRUCTION SET ADDITIONS AN
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APPENDIX B INPUT SYNCHRONIZATION Ma
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Instruction Set Descriptions C
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS INC IN
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INSTRUCTION SET DESCRIPTIONS OR OUT
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Instruction Set Opcodes and Clock C
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INSTRUCTION SET OPCODES AND CLOCK C
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INDEX 80C187 Math Coprocessor, 14-2
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INDEX registers, 6-5-6-15 system di
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INDEX port 2, 13-6 port 3, 13-7 pro
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INDEX P Packed BCD, defined, 2-37 P
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INDEX SCU asynchronous mode, 11-21-
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80C186EC/80C188EC Microprocessor User's Manual

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