80C186EC/80C188EC Microprocessor User's Manual

INDEX
registers, 6-5–6-15
system diagram, 6-16
See also Chip selects
Chip-selects
activating, 6-4
and 80C187 interface, 6-14, 14-11
and bus hold protocol, 6-15
and DMA acknowledge signal, 10-30
and DRAM controllers, 7-1
and guarded memory locations, 6-20
and reserved I/O locations, 6-14
enabling and disabling, 6-11
initializing, 6-6–6-15
methods for generating, 6-1
multiplexed I/O port pins, 13-6
overlapping, 6-12–6-14
programming considerations, 6-14
start address, 6-10, 6-14
stop address, 6-10
timing, 6-4
CL register, 2-5, 2-21, 2-22
CLKOUT
and bus hold, 5-6
and power management modes, 5-6
and reset, 5-6
Clock divider, 5-19
control register, 5-21
Clock generator, 5-6–5-10
and system reset, 5-6–5-7
output, 5-6
synchronizing CLKOUT and RESOUT, 5-6–
5-7
Clock sources, TCU, 9-12
Code (programs)‚ See Software
Code segment, 2-5
CompuServe forums, 1-6
Counters‚ See Timer Counter Unit (TCU)
CPU, block diagram, 2-2
Crystal‚ See Oscillator
CS register, 2-1, 2-5, 2-6, 2-13, 2-23, 2-39, 2-40,
2-41
Customer service, 1-4
CX register, 2-1, 2-5, 2-23, 2-25, 2-26
D
Data, 3-6
Data bus, See Address and data bus
Data segment, 2-5
Data sheets, obtaining from BBS, 1-6
Data transfers, 3-1–3-6
instructions, 2-18
PCB considerations, 4-5
PSW flag storage formats, 2-19
See also Bus cycles
Data types, 2-37–2-38
DI register, 2-1, 2-5, 2-13, 2-22, 2-23, 2-30, 2-32,
2-34
Digital one-shot, code example, 9-17–9-23
Direct Memory Access (DMA) Unit, 10-1–10-38
and BIU, 10-8
and CSU, 10-9
and PCB, 10-3
and SCU, 10-26, 10-30
arming channel, 10-23
DMA acknowledge signal, 10-2, 10-30
DRQ timing, 10-29
examples, 10-30–10-38
HALT bit, 10-27
HALT bits, 10-27
hardware considerations, 10-28–10-30
initialization code, 10-30–10-38
initializing, 10-27
Interrupt Request Latch Register (DMAIRL),
8-40
interrupts, 10-8
generating on terminal count, 10-25
introduction, 10-1
latency, 10-29
modules, 10-9–10-10, 10-12–10-14
multiplexed I/O port pins, 13-7
overview, 10-1–10-15
pointers, programming, 10-15–10-19
priority
channel, 10-9–10-10, 10-26
fixed, 10-9–10-11
module, 10-26–10-28
rotating, 10-11
programming, 10-22–10-27
arming channel, 10-23
channel priority, 10-26
initializing, 10-27
interrupts, 10-25
module priority, 10-26
source, 10-24
suspending transfers, 10-27
Index-3