80C186EC/80C188EC Microprocessor User's Manual

INPUT/OUTPUT PORTS
Register Name:
Register Mnemonic:
Register Function:
Port Pin State Register
PxPIN (P1PIN, P2PIN, P3PIN)
Reads the logic state at a port pin.
15 0
P
P
7
P
P
6
P
P
5
P
P
4
P
P
3
P
P
2
P
P
1
P
P
0
A1315-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
PP7:0
Port Pin
State 7:0
XXXXH
Reading the Port Pin State register returns the
logic state present on the associated pin.
NOTE: PP7 and PP6 do not exist for Port 3.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products.
Figure 13-7. Port Pin State Register (PxPIN)
13.2.5 Initializing the I/O Ports
The state of the I/O ports following a reset is as follows:
• Port 1 is configured for peripheral function (general-purpose chip-selects, GCS7:0).
• Port 2 is configured for peripheral function. The direction of each pin is the default direction
for the peripheral function (e.g., P2.5/TXD1 is an output, P2.2/BCLK0 is an input). See
Table 13-2 on page 13-6 for details.
• Ports P3.0 through P3.3 are configured for peripheral function (interrupt requests). Ports
P3.4 and P3.5 are configured as inputs (they are floating). See Table 13-3 on page 13-7 for
details.
There are no set rules for initializing the I/O ports. The Port Data Latch should be programmed
before selecting a pin as an output port (to prevent unknown Port Data Latch values from reaching
the pins).
13-11