80C186EC/80C188EC Microprocessor User's Manual

CHIP-SELECT UNIT
Register Name:
Register Mnemonic:
Register Function:
Chip-Select Stop Register
UCSSP, LCSSP, GCSxSP (x=0-7)
Defines chip-select stop address and other control
functions.
15 0
C
S
9
C
S
8
C
S
7
C
S
6
C
S
5
C
S
4
C
S
3
C
S
2
C
S
1
C
S
0
C
S
E
N
I
S
T
O
P
M
E
M
R
D
Y
A1164-0A
Bit
Mnemonic
Bit Name
Reset
State
Function
CS9:0
Stop
Address
3FFH
Defines the ending address for the chip-select.
CS9:0 are compared with the A19:10 (memory
bus cycles) or A15:6 (I/O bus cycles) address
bits. A less than result enables the chip-select.
CS9:0 are ignored if ISTOP is set.
CSEN
Chip-Select
Enable
0
(Note)
Disables the chip-select when cleared. Setting
CSEN enables the chip-select.
ISTOP
Ignore Stop
Address
0
(Note)
Setting this bit disables stop address checking,
which automatically sets the ending address at
0FFFFFH (memory) or 0FFFFH (I/O). When
ISTOP is cleared, the stop address requirements
must be met to enable the chip-select.
NOTE:
Reserved register bits are shown with gray shading. Reserved bits must be written
to a logic zero to ensure compatibility with future Intel products. The reset state of
CSEN and ISTOP is ‘1’ for the UCSSP register.
Figure 6-6. STOP Register Definition
6-8