80C186EC/80C188EC Microprocessor User's Manual

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DIRECT MEMORY ACCESS UNIT $mod186 name DMA_EXAMPLE_1 ; This example sets up the DMA Unit to perform a transfer from memory to ; I/O space every 22 uS. The data is sent to an A/D converter. ; It is assumed that the constants for PCB register addresses are ; defined elsewhere with EQUates. CODE_SEG SEGMENT ASSUME CS:CODE_SEG START: MOV AX, DATA_SEG ; DATA SEGMENT POINTER MOV DS, AX ASSUME DS:DATA_SEG ; First, set up the pointers. The source is in memory. MOV AX, SEG WAVEFORM_DATA ROL AX, 4 ; GET HIGH 4 BITS MOV BX, AX ; SAVE ROTATED VALUE AND AX, 0FFF0H ; GET SHIFTED LOW 4 NIBBLES ADD AX, OFFSET WAVEFORM_DATA ; NOW LOW BYTES OF POINTER ARE IN AX. ADC BX, 0 ; ADD IN THE CARRY ; TO THE HIGH NIBBLE AND BX, 000FH ; GET JUST THE HIGH NIBBLE MOV DX, D0SRCL OUT DX, AX ; AX=LOW 4 BYTES MOV DX, D0SRCH MOV AX, BX ; GET HIGH NIBBLE OUT DX, AX MOV AX, DA_CNVTR ; I/O ADDRESS OF D/A MOV DX, D0DSTL OUT DX, AX MOV DX, D0DSTH XOR AX, AX ; CLEAR HIGH NIBBLE OUT DX, AX ; THE POINTER ADDRESSES HAVE BEEN SET UP. NOW WE SET UP THE TRANSFER COUNT. ; PROGRAM IDRQ MUX MOV AX, 255 ; 8-BIT D/A, SO WE SEND 256 BYTES MOV DX, D0TC ; TO GET A FULL SCALE OUT DX, AX MOV DX, DMAPRI MOV AX, 00H ; TIMER2 IS IDRQ SOURCE ; MODULES HAVE EQUAL PRIORITY OUT DX, AX Example 10-3. Timed DMA Transfers 10-37
DIRECT MEMORY ACCESS UNIT ; NOW WE NEED TO SET THE PARAMETERS FOR THE CHANNEL AS FOLLOWS: ; ; DESTINATION SOURCE ; ----------- ------ ; I/O SPACE MEMORY SPACE ; CONSTANT PTR INCREMENT PTR ; ; TERMINATE ON TC, INTERRUPT, SOURCE SYNCHRONIZE, INTERNAL REQUESTS, ; LOW PRIORITY RELATIVE TO CHANNEL 1, BYTE XFERS. MOV MOV OUT AX, 0001011101010110B DX, D0CON DX, AX ; NOW WE ASSUME THAT TIMER 2 HAS BEEN PROPERLY PROGRAMMED FOR A 22uS DELAY. ; WHEN THE TIMER IS STARTED, A DMA TRANSFER WILL OCCUR EVERY 22uS. CODE_SEG DATA_SEG ENDS SEGMENT WAVEFORM_DATADB 0,1,2,3,4,5,6,7,8,9,10,11,12,13 DB 14,15,16,17,18,19,20,21,22,23,24 ; ETC., UP TO 255 DATA_SEG ENDS END START Example 10-3. Timed DMA Transfers (Continued) 10-38
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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Page 276 and 277: TIMER/COUNTER UNIT The timer counti
Page 278 and 279: TIMER/COUNTER UNIT Timer 0 Serviced
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Page 282 and 283: TIMER/COUNTER UNIT lib_80186 segmen
Page 284 and 285: TIMER/COUNTER UNIT $mod186 name exa
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Page 320 and 321: DIRECT MEMORY ACCESS UNIT $MOD186 n
Page 322 and 323: DIRECT MEMORY ACCESS UNIT SECTORS M
Page 324 and 325: DIRECT MEMORY ACCESS UNIT XOR AX, A
Page 328: Serial Communications Unit 11
Page 331 and 332: SERIAL COMMUNICATIONS UNIT 1 2 3 4
Page 333 and 334: SERIAL COMMUNICATIONS UNIT The RX m
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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INSTRUCTION SET DESCRIPTIONS NEG NO
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INSTRUCTION SET DESCRIPTIONS SHR ST
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APPENDIX D INSTRUCTION SET OPCODES
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INSTRUCTION SET OPCODES AND CLOCK C
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Index
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INDEX AH register, 2-5 AL register,
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INDEX synchronization, 10-23 transf
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INDEX NMI, 2-42 generating with WDT
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INDEX bus latency, 7-7 calculating
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INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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