80C186EC/80C188EC Microprocessor User's Manual

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INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Hex Byte 1 Binary Byte 2 Bytes 3–6 ASM-86 Instruction Format 2E 0010 1110 DS: (segment override prefix) 2F 0010 1111 das 30 0011 0000 mod reg r/m (disp-lo),(disp-hi) xor reg8/mem8,reg8 31 0011 0001 mod reg r/m (disp-lo),(disp-hi) xor reg16/mem16,reg16 32 0011 0010 mod reg r/m (disp-lo),(disp-hi) xor reg8,reg8/mem8 33 0011 0011 mod reg r/m (disp-lo),(disp-hi) xor reg16,reg16/mem16 34 0011 0100 data-8 xor AL,immed8 35 0011 0101 data-lo data-hi xor AX,immed16 36 0011 0110 SS: (segment override prefix) 37 0011 0111 aaa 38 0011 1000 mod reg r/m (disp-lo),(disp-hi) xor reg8/mem8,reg8 39 0011 1001 mod reg r/m (disp-lo),(disp-hi) xor reg16/mem16,reg16 3A 0011 1010 mod reg r/m (disp-lo),(disp-hi) xor reg8,reg8/mem8 3B 0011 1011 mod reg r/m (disp-lo),(disp-hi) xor reg16,reg16/mem16 3C 0011 1100 data-8 xor AL,immed8 3D 0011 1101 data-lo data-hi xor AX,immed16 3E 0011 1110 DS: (segment override prefix) 3F 0011 1111 aas 40 0100 0000 inc AX 41 0100 0001 inc CX 42 0100 0010 inc DX 43 0100 0011 inc BX 44 0100 0100 inc SP 45 0100 0101 inc BP 46 0100 0110 inc SI 47 0100 0111 inc DI 48 0100 1000 dec AX 49 0100 1001 dec CX 4A 0100 1010 dec DX 4B 0100 1011 dec BX 4C 0100 1100 dec SP 4D 0100 1101 dec BP 4E 0100 1110 dec SI 4F 0100 1111 dec DI 50 0101 0000 push AX 51 0101 0001 push CX 52 0101 0010 push DX D-11
INSTRUCTION SET OPCODES AND CLOCK CYCLES Table D-3. Machine Instruction Decoding Guide (Continued) Hex Byte 1 Binary Byte 2 Bytes 3–6 ASM-86 Instruction Format 53 0101 0011 push BX 54 0101 0100 push SP 55 0101 0101 push BP 56 0101 0110 push SI 57 0101 0111 push DI 58 0101 1000 pop AX 59 0101 1001 pop CX 5A 0101 1010 pop DX 5B 0101 1011 pop BX 5C 0101 1100 pop SP 5D 0101 1101 pop BP 5E 0101 1110 pop SI 5F 0101 1111 pop DI 60 0110 0000 pusha 61 0110 0001 popa 62 0110 0010 mod reg r/m bound reg16,mem16 63 0110 0011 — 64 0110 0100 — 65 0110 0101 — 66 0110 0110 — 67 0110 0111 — 68 0110 1000 data-lo data-hi push immed16 69 0110 1001 mod reg r/m data-lo, data-hi imul immed16 70 0111 0000 IP-inc-8 jo short-label 71 0111 0001 IP-inc-8 jno short-label 72 0111 0010 IP-inc-8 jb/jnae/jc short-label 73 0111 0011 IP-inc-8 jnb/jae/jnc short-label 74 0111 0100 IP-inc-8 je/jz short-label 75 0111 0101 IP-inc-8 jne/jnz short-label 76 0111 0110 IP-inc-8 jbe/jna short-label 77 0111 0111 IP-inc-8 jnbe/ja short-label 78 0111 1000 IP-inc-8 js short-label 79 0111 1001 IP-inc-8 jns short-label 7A 0111 1010 IP-inc-8 jp/jpe short-label 7B 0111 1011 IP-inc-8 jnp/jpo short-label 7C 0111 1100 IP-inc-8 jl/jnge short-label 7D 0111 1101 IP-inc-8 jnl/jge short-label D-12
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80C186EC/80C188EC Microprocessor Us
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Information in this document is pro
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CONTENTS 2.3 INTERRUPTS AND EXCEPTI
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CONTENTS 6.4 PROGRAMMING...........
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CONTENTS CHAPTER 9 TIMER/COUNTER UN
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CONTENTS 11.4 SERIAL COMMUNICATIONS
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CONTENTS FIGURES Figure Page 2-1 Si
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CONTENTS FIGURES Figure Page 6-6 ST
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CONTENTS FIGURES Figure Page 11-18
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CONTENTS Table TABLES Page C-1 Inst
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Introduction 1
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INTRODUCTION The 80C186 Modular Cor
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INTRODUCTION Table 1-2. Related Doc
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INTRODUCTION 1.3.2.1 How to Find Ap
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Overview of the 80C186 Family Archi
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OVERVIEW OF THE 80C186 FAMILY ARCHI
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Bus Interface Unit 3
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BUS INTERFACE UNIT Physical Impleme
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BUS INTERFACE UNIT (X + 1) (X) A19:
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BUS INTERFACE UNIT For word transfe
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BUS INTERFACE UNIT CLKOUT T4 T1 T2
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BUS INTERFACE UNIT CLKOUT T4 or TI
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BUS INTERFACE UNIT Signals From CPU
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BUS INTERFACE UNIT T2 T3 or TW T4 o
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BUS INTERFACE UNIT A normally not-r
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BUS INTERFACE UNIT T2 or T3 or TW T
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BUS INTERFACE UNIT An idle bus stat
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT T1 T2 T3 T4 CLKO
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BUS INTERFACE UNIT The minimum devi
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BUS INTERFACE UNIT Figure 3-24 show
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BUS INTERFACE UNIT After several TI
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BUS INTERFACE UNIT 3.5.5 Temporaril
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BUS INTERFACE UNIT CLKOUT ALE T4 T1
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BUS INTERFACE UNIT CLKOUT NMI/NTx N
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BUS INTERFACE UNIT ALE Processor A1
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BUS INTERFACE UNIT The WAIT instruc
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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BUS INTERFACE UNIT CLKOUT 1 3 4 HOL
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BUS INTERFACE UNIT CLKOUT HOLD 1 2
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Peripheral Control Block 4
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PERIPHERAL CONTROL BLOCK Register N
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PERIPHERAL CONTROL BLOCK 4.3 RESERV
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PERIPHERAL CONTROL BLOCK 4.4.3.1 Wr
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Clock Generation and Power Manageme
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CLOCK GENERATION AND POWER MANAGEME
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CHAPTER 6 CHIP-SELECT UNIT Every sy
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CHIP-SELECT UNIT Stop Value Ignore
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CHIP-SELECT UNIT Address 1 Ready Fl
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT Register Name: Reg
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CHIP-SELECT UNIT In the previous eq
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CHIP-SELECT UNIT No Any READY = 1 W
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CHIP-SELECT UNIT The GCS chip-selec
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CHIP-SELECT UNIT $ TITLE (Chip-Sele
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CHIP-SELECT UNIT ;SET UP CHIP SELEC
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Refresh Control Unit 7
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REFRESH CONTROL UNIT 7.1 THE ROLE O
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REFRESH CONTROL UNIT The BIU does n
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REFRESH CONTROL UNIT CLKOUT T4 T1 T
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REFRESH CONTROL UNIT 7.7.2.1 Refres
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REFRESH CONTROL UNIT Register Name:
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REFRESH CONTROL UNIT $mod186 name e
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REFRESH CONTROL UNIT T1 T1 T1 T1 T1
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CHAPTER 8 INTERRUPT CONTROL UNIT Th
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INTERRUPT CONTROL UNIT Polling requ
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INTERRUPT CONTROL UNIT INT INTA D7:
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INTERRUPT CONTROL UNIT Edge Sense L
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INTERRUPT CONTROL UNIT 8.3.2 Interr
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INTERRUPT CONTROL UNIT 8.3.3.1 Defa
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INTERRUPT CONTROL UNIT More than on
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INTERRUPT CONTROL UNIT IR0 IR1 IR2
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INTERRUPT CONTROL UNIT 10. On the s
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INTERRUPT CONTROL UNIT 8.3.7 Altern
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INTERRUPT CONTROL UNIT 8.4.2 Progra
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INTERRUPT CONTROL UNIT Begin Initia
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INTERRUPT CONTROL UNIT 8.4.3.3 ICW2
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INTERRUPT CONTROL UNIT Register Nam
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INTERRUPT CONTROL UNIT Table 8-2. O
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INTERRUPT CONTROL UNIT The ESMM (En
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INTERRUPT CONTROL UNIT Internal Int
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INTERRUPT CONTROL UNIT To Slave 825
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INTERRUPT CONTROL UNIT 8.6.1 Interr
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INTERRUPT CONTROL UNIT CPU WR RD GC
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INTERRUPT CONTROL UNIT Non-Alike Ac
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INTERRUPT CONTROL UNIT ;Now start t
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INTERRUPT CONTROL UNIT ;The followi
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CHAPTER 9 TIMER/COUNTER UNIT The Ti
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TIMER/COUNTER UNIT Timer 0 Timer 1
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TIMER/COUNTER UNIT Continued From "
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TIMER/COUNTER UNIT Register Name: R
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TIMER/COUNTER UNIT The timer counti
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TIMER/COUNTER UNIT Timer 0 Serviced
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TIMER/COUNTER UNIT 9.3.2 Synchroniz
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TIMER/COUNTER UNIT lib_80186 segmen
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TIMER/COUNTER UNIT $mod186 name exa
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TIMER/COUNTER UNIT _CMPB equ word p
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CHAPTER 10 DIRECT MEMORY ACCESS UNI
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DIRECT MEMORY ACCESS UNIT 10.1.1.1
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DIRECT MEMORY ACCESS UNIT The Chip-
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DIRECT MEMORY ACCESS UNIT Both Requ
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DIRECT MEMORY ACCESS UNIT Channel a
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DIRECT MEMORY ACCESS UNIT Register
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DIRECT MEMORY ACCESS UNIT When inte
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DIRECT MEMORY ACCESS UNIT The trans
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DIRECT MEMORY ACCESS UNIT 10.2.4 Su
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DIRECT MEMORY ACCESS UNIT 10.3.1 DR
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DIRECT MEMORY ACCESS UNIT $MOD186 n
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DIRECT MEMORY ACCESS UNIT SECTORS M
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DIRECT MEMORY ACCESS UNIT XOR AX, A
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DIRECT MEMORY ACCESS UNIT $mod186 n
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Serial Communications Unit 11
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SERIAL COMMUNICATIONS UNIT 1 2 3 4
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SERIAL COMMUNICATIONS UNIT The RX m
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SERIAL COMMUNICATIONS UNIT The Tran
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SERIAL COMMUNICATIONS UNIT 5. At th
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT Register
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SERIAL COMMUNICATIONS UNIT 3. If th
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SERIAL COMMUNICATIONS UNIT The seri
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SERIAL COMMUNICATIONS UNIT 11.2.3 P
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SERIAL COMMUNICATIONS UNIT BCLK is
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SERIAL COMMUNICATIONS UNIT $mod186
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT mov dx,
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SERIAL COMMUNICATIONS UNIT Disconne
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CHAPTER 12 WATCHDOG TIMER UNIT Syst
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WATCHDOG TIMER UNIT Figure 12-3(b)
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WATCHDOG TIMER UNIT wdt_data segmen
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WATCHDOG TIMER UNIT A LOCKed instru
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT Register Name:
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WATCHDOG TIMER UNIT wdt_data segmen
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CHAPTER 13 INPUT/OUTPUT PORTS Many
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INPUT/OUTPUT PORTS 13.1.2 Output Po
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INPUT/OUTPUT PORTS From Port Direct
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INPUT/OUTPUT PORTS 13.1.4.3 Port 3
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INPUT/OUTPUT PORTS Register Name: R
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INPUT/OUTPUT PORTS Register Name: R
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Math Coprocessing 14
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MATH COPROCESSING 14.3 THE 80C187 M
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MATH COPROCESSING Available data ty
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MATH COPROCESSING 14.3.1.5 Constant
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MATH COPROCESSING Increasing Signif
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MATH COPROCESSING 14.4.1 Clocking t
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MATH COPROCESSING External Oscillat
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MATH COPROCESSING 80C186 Modular Co
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MATH COPROCESSING $mod186 $modc187
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CHAPTER 15 ONCE MODE ONCE (pronounc
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APPENDIX A 80C186 INSTRUCTION SET A
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80C186 INSTRUCTION SET ADDITIONS AN
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Input Synchronization B
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INPUT SYNCHRONIZATION A synchroniza
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APPENDIX C INSTRUCTION SET DESCRIPT
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INSTRUCTION SET DESCRIPTIONS Table
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Page 442 and 443: INSTRUCTION SET DESCRIPTIONS Table
Page 462 and 463: INSTRUCTION SET DESCRIPTIONS NEG NO
Page 474 and 475: INSTRUCTION SET DESCRIPTIONS SHR ST
Page 478: INSTRUCTION SET DESCRIPTIONS Table
Page 482 and 483: APPENDIX D INSTRUCTION SET OPCODES
Page 484 and 485: INSTRUCTION SET OPCODES AND CLOCK C
Page 504: Index
Page 507 and 508: INDEX AH register, 2-5 AL register,
Page 509 and 510: INDEX synchronization, 10-23 transf
Page 511 and 512: INDEX NMI, 2-42 generating with WDT
Page 513 and 514: INDEX bus latency, 7-7 calculating
Page 515: INDEX Trap exceptions, 2-42 Trap Fl
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80C186EC/80C188EC Microprocessor User's Manual

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