80C186EC/80C188EC Microprocessor User's Manual

CLOCK GENERATION AND POWER MANAGEMENT
5.2.2.1 Entering Powerdown Mode
Powerdown mode is entered by executing the HLT instruction after setting the PWRDN bit in the
Power Control Register (see Figure 5-9 on page 5-12). The HALT cycle turns off both the core
and peripheral clocks and disables the crystal oscillator. See Chapter 3, “Bus Interface Unit,” for
detailed information on HALT bus cycles. Figure 5-12 shows the internal and external waveforms
during entry into Powerdown mode.
CLKIN
OSCOUT
CLKOUT
CPU Core
Clock
Internal
Peripheral
Clock
Halt Cycle
T4 or T1 T1 T2 TI
CLKIN toggles
only when
external
frequency
input is used
Indeterminate
S2:0
ALE
011
A1121-0A
Figure 5-12. Entering Powerdown Mode
During the T2 phase of the HLT instruction, the core generates a signal called Enter_Powerdown.
Enter_Powerdown immediately disables the internal CPU core and peripheral clocks. The processor
disables the oscillator inverter during the next CLKOUT cycle. If the design uses a crystal
oscillator, the oscillator stops immediately. When CLKIN originates from an external frequency
input (EFI), Powerdown isolates the signal on the CLKIN pin from the internal circuitry. Therefore,
the circuit may drive CLKIN during Powerdown mode, although it will not clock the device.
5-17